Memory devices and methods of forming memory devices

ABSTRACT

A memory device may be provided, including a base insulating layer, a bottom electrode arranged within the base insulating layer, a substantially planar switching layer arranged over the base insulating layer and a substantially planar top electrode arranged over the switching layer in a laterally offset position relative to the bottom electrode.

TECHNICAL FIELD

The present disclosure relates generally to memory devices and methods of forming the memory devices.

BACKGROUND

Non-volatile memory devices are often used in consumer electronic products such as smart phones and tablets. One type of non-volatile memory device is the resistive random access memory device (RRAM). A RRAM typically uses a switching layer such as a dielectric layer sandwiched between a top electrode and a bottom electrode. The switching layer is normally insulating. However, upon application of a sufficiently high potential difference between the top and bottom electrodes, a dielectric breakdown event can occur and conducting filaments may be formed within the switching layer between the top and bottom electrodes. The switching layer thus becomes conductive via the conducting filaments. The switching layer can be made insulating again by applying a sufficiently low voltage difference to the top and bottom electrodes to break the conducting filaments. A typical RRAM can switch between states based on the resistance of the switching layer. When the switching layer is insulating, the switching layer has a high resistance, and the RRAM may be referred to as being in a high resistance state (HRS). When the switching layer is conductive, the switching layer has a low resistance and the RRAM may be referred to as being in a low resistance state (LRS). To set the RRAM, the RRAM is switched from the HRS to the LRS. To reset the RRAM, the RRAM is switched from the LRS to the HRS.

Conducting filaments are often formed at random across many locations within the switching layer. Such uncontrolled distribution of the conducting filaments can cause the resistance of the switching layer (and hence, the RRAM) to vary greatly across multiple dielectric breakdown events. For example, the resistance of the switching layer when the RRAM is in the HRS tends to vary greatly over different cycles. This can lead to high device-to-device variability and cycle-to-cycle variability.

Accordingly, it is desirable to provide an improved memory device having reduced variability in its resistance.

SUMMARY

According to various non-limiting embodiments, there may be provided a memory device including a base insulating layer, a bottom electrode arranged within the base insulating layer, a substantially planar switching layer arranged over the base insulating layer and a substantially planar top electrode arranged over the switching layer in a laterally offset position relative to the bottom electrode.

According to various non-limiting embodiments, there may be provided a memory device including a base insulating layer, a bottom electrode arranged within the base insulating layer, a substantially planar switching layer arranged over the base insulating layer and a substantially planar top electrode arranged over the switching layer in a laterally offset position relative to the bottom electrode. A bottom edge between a bottom surface and a side surface of the top electrode, and a top edge between a top surface and a side surface of the bottom electrode may be spaced apart by a distance at least equal to a thickness of the switching layer.

According to various non-limiting embodiments, there may be provided a method of fabricating a memory device. The method may include providing a base insulating layer, forming a bottom electrode within the base insulating layer, forming a substantially planar switching layer over the base insulating layer and forming a substantially planar top electrode over the switching layer in a laterally offset position relative to the bottom electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. Non-limiting embodiments of the invention will now be illustrated for the sake of example only with reference to the following drawings, in which:

FIGS. 1A, 1B and 1C respectively show a simplified perspective view, a simplified top view and a simplified cross-sectional view of a memory device according to various non-limiting embodiments;

FIG. 2 shows simulated electric fields in the memory device of FIGS. 1A to 1C;

FIGS. 3A to 3D show simplified cross-sectional views that illustrate a method for fabricating a plurality of the memory devices of FIGS. 1A to 1C according to various non-limiting embodiments;

FIGS. 4A and 4B respectively show a simplified perspective view and a simplified top view of a memory device according to alternative non-limiting embodiments;

FIG. 5 shows simulated electric fields in the memory device of FIGS. 4A and 4B;

FIGS. 6A, 6B and 6C respectively show a simplified perspective view, a simplified top view and a simplified cross-sectional view of a memory device according to alternative non-limiting embodiments;

FIGS. 7A to 7C show simulated electric fields of memory devices similar to the memory device of FIGS. 6A to 6C, but with different overlap distances between the top and bottom electrodes;

FIG. 8 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIGS. 9A, 9B and 9C respectively show a simplified perspective view, a simplified top view and a simplified cross-sectional view of a memory device according to alternative non-limiting embodiments;

FIGS. 10A to 10C show simulated electric fields in memory devices similar to the memory device of FIGS. 9A to 9C, but with different spacings between the top and bottom electrodes;

FIG. 11 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIGS. 12A and 12B respectively show a simplified top view and a simplified cross-sectional view of a memory device according to alternative non-limiting embodiments;

FIGS. 13A and 13B show simulated electric fields in the memory device of FIGS. 12A and 12B;

FIGS. 14A and 14B respectively show a simplified top view and a simplified cross-sectional view of a memory device according to alternative non-limiting embodiments;

FIG. 15 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIG. 16 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIG. 17 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIGS. 18A and 18B show simulated electric fields in the memory device of FIG. 17;

FIG. 19 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIGS. 20A, 20B and 20C respectively show a simplified perspective view, a simplified top view and a simplified cross-sectional view of a memory device according to alternative non-limiting embodiments;

FIG. 21 shows simulated electric fields in the memory device of FIGS. 20A to 20C;

FIG. 22 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIG. 23 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIGS. 24A and 24B show simulated electric fields in the memory device of FIG. 23;

FIG. 25 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIGS. 26A and 26B show simulated electric fields in the memory device of FIG. 25;

FIG. 27 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIG. 28 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIG. 29 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIGS. 30A and 30B show simulated electric fields in the memory device of FIG. 29;

FIG. 31 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIG. 32 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIGS. 33A and 33B show simulated electric fields in the memory device of FIG. 32;

FIG. 34 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIGS. 35A and 35B show simulated electric fields in the memory device of FIG. 34;

FIG. 36 shows a simplified top view of a memory device according to alternative non-limiting embodiments;

FIG. 37 shows a simplified top view of a memory device according to alternative non-limiting embodiments; and

FIGS. 38A and 38B respectively show simulated electric fields in a memory structure including the memory devices of FIGS. 6A to 6C and a memory structure including the memory devices of FIGS. 9A to 9B.

DETAILED DESCRIPTION

The embodiments generally relate to semiconductor devices. More particularly, some embodiments relate to memory devices, for instance, non-volatile memory devices such as RRAM devices in a non-limiting example. The memory devices may be used in several applications, such as, but not limited to, neuromorphic computing applications and multi-bit applications.

Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating aspects of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and/or arrangements, within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure.

Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Further, a direction is modified by a term or terms, such as “substantially” to mean that the direction is to be applied within normal tolerances of the semiconductor industry. For example, “substantially parallel” means largely extending in the same direction within normal tolerances of the semiconductor industry and “substantially perpendicular” means at an angle of ninety degrees plus or minus a normal tolerance of the semiconductor industry.

The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include (and any form of include, such as “includes” and “including”), and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises,” “has,” “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises,” “has,” “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.

As used herein, the term “connected,” when used to refer to two physical elements, means a direct connection between the two physical elements. The term “coupled,” however, can mean a direct connection or a connection through one or more intermediary elements.

As used herein, the terms “may” and “may be” indicate a possibility of an occurrence within a set of circumstances; a possession of a specified property, characteristic or function; and/or qualify another verb by expressing one or more of an ability, capability, or possibility associated with the qualified verb. Accordingly, usage of “may” and “may be” indicates that a modified term is apparently appropriate, capable, or suitable for an indicated capacity, function, or usage, while taking into account that in some circumstances the modified term may sometimes not be appropriate, capable or suitable. For example, in some circumstances, an event or capacity can be expected, while in other circumstances the event or capacity cannot occur—this distinction is captured by the terms “may” and “may be.”

FIG. 1A shows a simplified perspective view of a memory device 100 according to various non-limiting embodiments. FIG. 1B shows a simplified top view of the memory device 100 and FIG. 1C shows a cross-sectional view of the memory device 100 along the line A-A′ of FIG. 1B. The memory device 100 may be a RRAM device.

As shown in FIG. 1A, the memory device 100 may include a base insulating layer 102. The base insulating layer 102 may extend along a horizontal plane defined by an X-axis and a Y-axis. The base insulating layer 102 may be an inter-layer dielectric (ILD) layer and may include insulating material, such as, but not limited to, silicon oxide, silicon dioxide, silicon nitride, or combinations thereof.

The memory device 100 may further include a bottom electrode 104 arranged within the base insulating layer 102. As shown in FIGS. 1A to 1C, the bottom electrode 104 may be a cuboid with six surfaces including a top surface 104 a, a bottom surface 104 b, side surfaces (including a left surface 104 c and a right surface 104 d), a front surface 104 e and a back surface 104 f. The left and right surfaces 104 c, 104 d of the bottom electrode 104 may be substantially parallel to the Y-axis and substantially perpendicular to the X-axis. The front surface 104 e may adjoin the side (left and right) surfaces 104 c, 104 d. The bottom electrode 104 may include inert electrode material, such as, but not limited to, ruthenium (Ru), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), alloys thereof or combinations thereof. A thickness T₁₀₄ of the bottom electrode 104 may range from about 3 nm to about 15 nm, and in a non-limiting embodiment, may range from about 5 nm to about 10 nm. A width W₁₀₄ and a length L₁₀₄ of the bottom electrode 104 may be approximately the same, and may range from about 20 nm to about 100 nm, and may be about 30 nm in a non-limiting embodiment.

The memory device 100 may also include a substantially planar switching layer 106 arranged over the base insulating layer 102. The switching layer 106 may include switching material, such as, but not limited to, magnesium oxide (MgO), tantalum oxide (TaO₂), hafnium oxide (HfO₂), titanium oxide (TiO₂), aluminum oxide (AlO₂), silicon dioxide (SiO₂) or combinations thereof. A thickness T₁₀₆ of the switching layer 106 may range from about 1 nm to about 15 nm, and in a non-limiting embodiment, may range from about 2 nm to about 10 nm.

In addition, the memory device 100 may include a substantially planar top electrode 108 arranged over the switching layer 106. In FIGS. 1A to 1C, the switching layer 106 is depicted as extending under the top electrode 108 and over the bottom electrode 104. However, the switching layer 106 may alternatively extend under only the top electrode 108 and not over the bottom electrode 104. For example, an additional insulating layer (e.g. a dielectric layer) may be provided over the base insulating layer 102 and the switching layer 106 may be arranged within this additional insulating layer under only the top electrode 108.

The top electrode 108 may also be a cuboid with six surfaces including a top surface 108 a, a bottom surface 108 b, side surfaces (including a left surface 108 c and a right surface 108 d), a front surface 108 e and a back surface 108 f. The left and right surfaces 108 c, 108 d of the top electrode 108 may be substantially parallel to the Y-axis and substantially perpendicular to the X-axis. The front surface 108 e may adjoin the side (left and right) surfaces 108 c, 108 d. The top electrode 108 may include active electrode material such as, but not limited to, tantalum (Ta), hafnium (Hf), titanium (Ti), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), alloys thereof or combinations thereof. A thickness T₁₀₈ of the top electrode 108 may range from about 3 nm to about 35 nm, and in a non-limiting embodiment, may range from about 5 nm to about 30 nm. Further, a width W₁₀₈ and a length L₁₀₈ of the top electrode 108 may be approximately the same, and may range from about 20 nm to about 100 nm, and may be about 30 nm in a non-limiting embodiment. The width W₁₀₈ and length L₁₀₈ of the top electrode 108 may be approximately equal to the width W₁₀₄ and length L₁₀₄ of the bottom electrode 104 respectively. In other words, the sizes of the top and bottom electrodes 108, 104 may be the same. However, the sizes of the top and bottom electrodes 108, 104 may alternatively be different.

As shown in FIGS. 1A to 1C, the right surface 104 d of the bottom electrode 104 may face a first direction 150 and the left surface 108 c of the top electrode 108 may face a second direction 152 opposite the first direction 150. The bottom surface 108 b of the top electrode 108 may face the base insulating layer 102 and the top surface 104 a of the bottom electrode 104 may face an opposite direction from the bottom surface 108 b of the top electrode 108. Further, the front surfaces 104 e, 108 e of the bottom and top electrodes 104, 108 may face a same (third) direction 154, and the back surfaces 104 f, 108 f may face a same (fourth) direction 156.

The top electrode 108 may be in a laterally offset position relative to the bottom electrode 104. “Laterally offset” is defined herein to mean that at most a part of the bottom surface 108 b of the top electrode 108 may overlap with the top surface 104 a of the bottom electrode 104, and at most a part of the top surface 104 a of the bottom electrode 104 may overlap with the bottom surface 108 b of the top electrode 108. For instance, as shown in FIGS. 1A to 1C, the top and bottom electrodes 108, 104 may be laterally offset with respect to each other along the X-axis. In particular, the top electrode 108 may extend in the first direction 150 away from the right surface 104 d of the bottom electrode 104, and the bottom electrode 104 may extend in the second direction 152 away from the left surface 108 c of the top electrode 108. Said differently, “laterally offset” includes embodiments where a first specified surface partially overlaps with a second specified surface, or where such first specified surface does not overlap with the second specified surface and/or where a space is arranged between the first specified surface and the second specified surface. For example, here where at most a part of the bottom surface 108 b of the top electrode 108 may overlap with the top surface 104 a of the bottom electrode 104 includes where the bottom surface 108 b only partially overlaps with the top surface 104 a or where the bottom surface 108 b does not overlap with the top surface 104 a. Similarly, here where at most a part of the top surface 104 a of the bottom electrode 104 may overlap with the bottom surface 108 b of the top electrode 108 includes where the top surface 104 a only partially overlaps with the bottom surface 108 b or where the top surface 104 a does not overlap with the bottom surface 108 b. “Laterally offset” further means that the two electrodes 104, 108 are not arranged in the same vertical plane.

Referring to FIG. 1A, the top electrode 108 may include a bottom edge Ebc₁₀₈; whereas, the bottom electrode 104 may include a top edge Ead₁₀₄. In this document, an edge Exy_(I) refers to an edge adjoining the surface Ix and the surface Iy of the electrode I. For example, the edge Ebc₁₀₈ adjoins the bottom surface 108 b and the side (left) surface 108 c of the top electrode 108; whereas, the edge Ead₁₀₄ adjoins the top surface 104 a and the side (right) surface 104 d of the bottom electrode 104. As further shown in FIG. 1A, the bottom edge Ebc₁₀₈ of the top electrode 108 and the top edge Ead₁₀₄ of the bottom electrode 104 may at least partially extend along a same first vertical plane 158. In this document, by “vertical”, it is meant that the plane or axis may be substantially perpendicular to the base insulating layer 102 and the switching layer 106. Accordingly, the top surface 104 a of the bottom electrode 104 and the bottom surface 108 b of the top electrode 108 may overlap each other at only the edges Ebc₁₀₈, Ead₁₀₄. A distance D_(LR) parallel to the X-axis between the opposite facing surfaces 104 d, 108 c may be smaller than a distance D_(LL) parallel to the X-axis between the left surfaces 104 c, 108 c and a distance D_(RR) parallel to the X-axis between the right surfaces 104 d, 108 d. In particular, the distance D_(LR) may be approximately 0 nm; whereas the distances D_(LL), D_(RR) may be approximately equal to the length L₁₀₄ of the bottom electrode 104 and the length L₁₀₈ of the top electrode 108, respectively.

Further, as shown in FIGS. 1A to 1C, the top and bottom electrodes 108, 104 may be laterally aligned along the Y-axis. In particular, the front surface 108 e of the top electrode 108 and the front surface 104 e of the bottom electrode 104 may at least partially extend along a same second vertical plane 160. The second vertical plane 160 may be substantially perpendicular to the first vertical plane 158.

Referring to FIG. 1C, a conductive line 112 may be arranged over the top electrode 108. The conductive line 112 may serve as a bit line and may include conductive material, such as, but not limited to, aluminum, copper, tungsten, alloys thereof, or combinations thereof. A connector 110 may be arranged between the conductive line 112 and the top electrode 108 to electrically connect the conductive line 112 with the top electrode 108. The connector 110 may similarly include conductive material, such as, but not limited to, aluminum, copper, tungsten, alloys thereof, or combinations thereof.

As shown in FIG. 1C, the memory device 100 may in addition include a further insulating layer 114. The top electrode 108, the connector 110 and the conductive line 112 may be arranged within the further insulating layer 114. The further insulating layer 114 may include insulating material, such as, but not limited to silicon oxide, silicon dioxide, silicon nitride or combinations thereof.

Note that for clarity of illustration, the further insulating layer 114, the connector 110 and the conductive line 112 are not shown in FIGS. 1A and 1B and some reference numerals are omitted from FIG. 1A.

Referring to FIG. 1C, the top electrode 108 may be arranged relative to the bottom electrode 104 to allow formation of conducting filaments 180 between the top electrode 108 and the bottom electrode 104. In particular, when a sufficiently large potential difference is applied between the top and bottom electrodes 104, 108 of the memory device 100, conducting filaments 180 may be formed between these electrodes 104, 108. The conducting filaments 180 may be confined between the bottom edge Ebc₁₀₈ of the top electrode 108 and the top edge Ead₁₀₄ of the bottom electrode 104, as the electric fields at these edges Ead₁₀₄, Ebc₁₀₈ may be higher than that at other parts of the memory device 100.

FIG. 2 shows simulated electric fields formed in the memory device 100 when a sufficiently large potential difference is applied between the top and bottom electrodes 104, 108. For clarity of illustration, some reference numerals have been omitted from FIG. 2. As shown in FIG. 2, the simulated electric field strengths at the top edge Ead₁₀₄ of the bottom electrode 104 and at the bottom edge Ebc₁₀₈ of the top electrode 108 are higher than that at other parts of the memory device 100. In particular, the simulated electric field strength at the edge Ead₁₀₄ is approximately 2.83×10⁸V/m and the simulated electric field strength at the edge Ebc₁₀₈ is approximately 5.99×10⁸V/m. Accordingly, conducting filaments (e.g. conducting filaments 180 in FIG. 1C) may be confined between the edges Ead₁₀₄, Ebc₁₀₈ where the strengths of the electric fields are the highest.

FIGS. 3A to 3D show simplified cross-sectional views that illustrate a method for fabricating a plurality of the memory devices 100 according to various non-limiting embodiments. Similarly, for clarity of illustration, some reference numerals are omitted from FIGS. 3A to 3D.

Referring to FIG. 3A, the method may include forming the base insulating layer 102 and the bottom electrodes 104 within the base insulating layer 102. The bottom electrodes 104 may be formed by first depositing inert electrode material over a surface above which the memory device 100 is to be formed, and then selectively etching the inert electrode material using for example, a photoresist mask. The base insulating layer 102 may be formed by depositing insulating material over and between the bottom electrodes 104, and planarizing the insulating material using, for example, a chemical mechanical planarization (CMP) process.

Referring to FIG. 3B, the method may further include forming the switching layer 106 above the base insulating layer 102. The switching layer 106 may be formed by depositing switching material over the base insulating layer 102 and the bottom electrodes 104.

Referring to FIG. 3C, the method may further include forming the top electrodes 108 above the switching layer 106, and forming the connectors 110 over the respective top electrodes 108. The top electrodes 108 and the connectors 110 may be formed by depositing active electrode material over the switching layer 106 and conductive material over the active electrode material, and then selectively etching the active electrode material and the conductive material using for example, an etch down process.

Referring to FIG. 3D, the method may further include forming the conductive lines 112 over the respective connectors 110 and forming the further insulating layer 114. A first part of the further insulating layer 114 may be formed by depositing first insulating material over the top electrodes 108, the connectors 110 and the switching layer 106, and then planarizing the first insulating material (using for example, a CMP process), so that the top surface of the first insulating material may be level with the top surfaces of the connectors 110. The conductive lines 112 may then be formed over the connectors 110 using any process as known to those skilled in the art. For example, the conductive lines 112 may be formed by depositing conductive material over the connectors 110 and the first insulating material, and selectively etching the conductive material. A second part of the further insulating layer 114 may then be formed by depositing second insulating material over the conductive lines 112 and the first insulating material, and planarizing the second insulating material (using, for example, a CMP process), so that the top surface of the second insulating material may be level with the top surfaces of the conductive lines 112.

The above described order for the method is only intended to be illustrative, and the method is not limited to the above specifically described order unless otherwise specifically stated.

FIG. 4A shows a simplified perspective view of a memory device 400 according to alternative non-limiting embodiments. FIG. 4B shows a simplified top view of the memory device 400. The memory device 400 is similar to the memory device 100, and thus, the common features are labelled with the same reference numerals and need not be discussed.

Similar to the memory device 100, in the memory device 400, the bottom edge Ebc₁₀₈ of the top electrode and the top edge Ead₁₀₄ of the bottom electrode 104 may at least partially extend along a same first vertical plane 158. However, the top and bottom electrodes 108, 104 of the memory device 400 may be laterally offset from each other along both the X-axis and the Y-axis. In other words, referring to FIG. 4B, the front surface 108 e of the top electrode 108 and the front surface 104 e of the bottom electrode 104 may at least partially extend along different second and third vertical planes 162, 164 respectively. These second and third vertical planes 162, 164 may be substantially parallel to each other and substantially perpendicular to the first vertical plane 158. In addition, the second and third vertical planes 162, 164 may be laterally spaced apart from each other. For clarity of illustration, these vertical planes 162, 164 are not shown in FIG. 4A.

Further, referring to FIG. 4A, in the memory device 400, a corner Cade₁₀₄ of the bottom electrode 104 may be vertically aligned with a corner Cbcf₁₀₈ of the top electrode 108 along a vertical axis 402. In this document, a corner Cxyz_(I) refers to a corner adjoining the surfaces Ix, Iy and Iz of the electrode I. For example, the corner Cade₁₀₄ adjoins the front surface 104 e with two other surfaces (the right surface 104 d and the top surface 104 a) of the bottom electrode 104; whereas, the corner Cbcf₁₀₈ adjoins the back surface 108 f with two other surfaces (the bottom surface 108 b and the left surface 108 c) of the top electrode 108. The top electrode 108 and the bottom electrode 104 may extend substantially parallel to the vertical plane 158 away from the vertical axis 402 in opposite directions 154, 156, with the top electrode 108 extending in the third direction 154 and the bottom electrode 104 extending in the fourth direction 156.

FIG. 5 shows simulated electric fields formed in the memory device 400 when a sufficiently large potential difference is applied between the top and bottom electrodes 104, 108. For clarity of illustration, some reference numerals are omitted in FIG. 5. As shown in FIG. 5, the simulated electric field strength along the vertical axis 402, and between the corner Cade₁₀₄ of the bottom electrode 104 and the corner Cbcf₁₀₈ of the top electrode 108 is higher than the simulated electric field strengths at other parts of the memory device 400. In particular, the simulated electric field strength at the corner Cade₁₀₄ of the bottom electrode 104 is approximately 2.52×10⁸V/m and the simulated electric field strength at the corner Cbcf₁₀₈ of the top electrode 108 is approximately 3.77×10⁸V/m. Therefore, conducting filaments may be formed and confined between these corners Cade₁₀₄, Cbcf₁₀₈ where the electric fields have the highest strengths.

In the memory devices 100, 400, the bottom edge Ebc₁₀₈ of the top electrode 108 and the top edge Ead₁₀₄ of the bottom electrode 104 may at least partially extend along a same vertical plane 158. However, in alternative non-limiting embodiments, the bottom edge Ebc₁₀₈ of the top electrode 108 and the top edge Ead₁₀₄ of the bottom electrode 104 may at least partially extend along different vertical planes laterally offset from each other. For example, the bottom surface 108 b of the top electrode 108 may partially overlap with the top surface 104 a of the bottom electrode 104, or the entire bottom surface 108 b of the top electrode 108 and the entire top surface 104 a of the bottom electrode 104 may be laterally spaced apart.

FIG. 6A shows a simplified perspective view of a memory device 600 according to alternative non-limiting embodiments. FIG. 6B shows a simplified top view of the memory device 600 and FIG. 6C shows a simplified cross-sectional view of the memory device 600 along the line B-B′ of FIG. 6B. The memory device 600 is similar to the memory device 100, and thus, the common features are labelled with the same reference numerals and need not be discussed.

As shown in FIGS. 6A to 6C, in the memory device 600, the top edge Ead₁₀₄ of the bottom electrode 104 and the bottom edge Ebc₁₀₈ of the top electrode 108 may at least partially extend along different first and second vertical planes 604, 608, respectively. The vertical planes 604, 608 may be substantially parallel to and laterally spaced apart from each other. In particular, the bottom surface 108 b of the top electrode 108 may partially overlap with the top surface 104 a of the bottom electrode 104 by an overlap distance 602 parallel to the X-axis. The overlap distance 602 may be less than or equal to 50 nm, and may be less than or equal to 30 nm in some non-limiting embodiments. For example, the overlap distance 602 may be about 10 nm, about 20 nm, or about 30 nm in a first, a second and a third non-limiting embodiment. A distance D_(LR) parallel to the X-axis between the left surface 108 c of the top electrode 108 and the right surface 104 d of the bottom electrode 104 may be equal to the overlap distance 602, and may be smaller than a distance D_(LL) between the left surfaces 108 c, 104 c of the electrodes 108, 104 and a distance D_(RR) between the right surfaces 108 d, 104 d of the electrodes 108, 104.

As shown in FIGS. 6A and 6B, the top and bottom electrodes 108, 104 may be laterally offset with respect to each other along the X-axis but laterally aligned along the Y-axis. Accordingly, the front surface 104 e of the bottom electrode 104 and the front surface 108 e of the top electrode 108 may at least partially extend along a same third vertical plane 610. The third vertical plane 610 may be substantially perpendicular to the first and second vertical planes 604, 608.

Referring to FIG. 6C, when a sufficiently large potential difference is applied between the top and bottom electrodes 104, 108, conducting filaments 180 may be formed between the top and bottom electrodes 104, 108. The conducting filaments 180 may be confined between the top edge Ead₁₀₄ of the bottom electrode 104 and the bottom edge Ebc₁₀₈ of the top electrode 108, as the electric fields at these edges Ead₁₀₄, Ebc₁₀₈ may be higher than that at other parts of the memory device 600.

The minimum electric field strength required to form conducting filaments 180 between the top and bottom electrodes 104, 108 in the memory device 600 may be determined using the following Equation (1).

$\begin{matrix} {{{Minimum}\mspace{14mu}{electric}\mspace{14mu}{field}} = \frac{\begin{matrix} {{Potential}\mspace{14mu}{difference}\mspace{14mu}{between}} \\ {{the}\mspace{14mu}{top}\mspace{14mu}{and}\mspace{14mu}{bottom}\mspace{14mu}{electrodes}} \end{matrix}}{\begin{matrix} \begin{matrix} \begin{matrix} {{Distance}\mspace{14mu}{between}\mspace{14mu}{the}\mspace{14mu}{top}\mspace{14mu}{edge}\mspace{14mu}{Ead}_{104}} \\ {{of}\mspace{14mu}{the}\mspace{14mu}{bottom}\mspace{14mu}{electrode}} \end{matrix} \\ {{and}\mspace{14mu}{the}\mspace{14mu}{bottom}\mspace{14mu}{edge}\mspace{14mu}{Ebc}_{108}} \end{matrix} \\ {{of}\mspace{14mu}{the}\mspace{14mu}{top}\mspace{14mu}{electrode}} \end{matrix}}} & (1) \end{matrix}$

The distance between the top edge Ead₁₀₄ of the bottom electrode 104 and the bottom edge Ebc₁₀₈ of the top electrode 108 may be determined using Equation (2) as follows, where the horizontal distance between the electrodes 104, 108 may be the distance D_(LR) parallel to the X-axis between the left surface 108 c of the top electrode 108 and the right surface 104 d of the bottom electrode 104. As shown by Equation (2), the edges Ead₁₀₄, Ebc₁₀₈ may be spaced apart by a distance at least equal to a thickness T₁₀₆ of the switching layer.

$\begin{matrix} {{{Distance}\mspace{14mu}{between}\mspace{14mu}{the}\mspace{14mu}{top}\mspace{14mu}{edge}\mspace{14mu}{Ead}_{104}\mspace{14mu}{of}\mspace{14mu}{the}\mspace{14mu}{bottom}\mspace{14mu}{electrode}\mspace{14mu}{and}\mspace{14mu}{the}\mspace{14mu}{bottom}\mspace{14mu}{edge}\mspace{14mu}{Ebc}_{108}\mspace{14mu}{of}\mspace{14mu}{the}\mspace{14mu}{top}\mspace{14mu}{electrode}} = \sqrt{\begin{matrix} {\left( {{Thickness}\mspace{14mu} T_{106}\mspace{14mu}{of}\mspace{14mu}{the}\mspace{14mu}{switching}\mspace{14mu}{layer}} \right)^{2} +} \\ \left( {{Horizontal}\mspace{14mu}{distance}\mspace{14mu}{between}\mspace{14mu}{the}\mspace{14mu}{electrodes}} \right)^{2} \end{matrix}}} & (2) \end{matrix}$

The lengths of the conducting filaments 180 formed between the top and bottom electrodes 104, 108 may be approximately equal to the distance between the edges Ead₁₀₄, Ebc₁₀₈ determined using Equation (2).

FIGS. 7A to 7C show simulated electric fields formed in memory devices 700, 702, 704 when a sufficiently large potential difference is applied between the top and bottom electrodes 104, 108 of each memory device 700, 702, 704. For ease of illustration, some reference numerals are omitted from FIGS. 7A to 7C.

The memory devices 700, 702, 704 may be similar to the memory device 600 but with different overlap distances 602 of 10 nm, 20 nm, 30 nm, respectively. The simulated electric fields in FIGS. 7A to 7C were obtained with a thickness T₁₀₆ of each switching layer 106 set as 5 nm and a potential difference between the top and bottom electrodes 104, 108 set as 2V. Using the above Equation (2), the length of the conducting filaments (e.g. conducting filaments 180 as shown in FIG. 6C) may be determined as 11.2 nm, 20.6 nm and 30.4 nm when the overlap distance 602 is 10 nm, 20 nm, or 30 nm respectively. Using the above Equation (1), the minimum electric field strength to form such conducting filaments in the memory device 700, 702, 704 may be determined as 1.79×10⁸V/m, 9.7×10⁷V/m and 6.58×10⁷V/m respectively.

As shown in FIGS. 7A to 7C, in each memory device 700, 702, 704, the simulated electric field strength at the top edge Ead₁₀₄ of the bottom electrode 104 and at the bottom edge Ebc₁₀₈ of the top electrode 108 may be higher than the simulated electric field strengths at other parts of the memory device 700, 702, 704. In particular, when the overlap distance 602 is 10 nm, 20 nm, or 30 nm, the simulated electric field strength at the top edge Ead₁₀₄ of the bottom electrode 104 is approximately 3.23×10⁸V/m, 3.07×10⁸V/m and 2.74×10⁸V/m respectively; whereas, the simulated electric field strength at the bottom edge Ebc₁₀₈ of the top electrode 108 is approximately 6.38×10⁸V/m, 6.72×10⁸V/m and 6.64×10⁸V/m respectively. Comparing these simulated electric field strengths with the above-mentioned minimum electric field strengths determined using Equation (1), conducting filaments may be formed in the memory devices 700, 702, 704. Further, the electric field strength at the portion 705 of the bottom electrode 104 below the edge Ebc₁₀₈ of the top electrode 108 in the memory device 700, 702, 704 is only about 2.12×10⁸V/m, 2.16×10⁸V/m and 2.16×10⁸V/m respectively. Similarly, the electric field strength at the portion 709 of the top electrode 108 above the edge Ead₁₀₄ of the bottom electrode 104 in the memory device 700, 702, 704 is only about 2.28×10⁸V/m, 2.27×10⁸V/m and 2.27×10⁸V/m respectively. Accordingly, the conducting filaments (e.g. conducting filaments 180 in FIG. 6C) may be formed and confined between the edges Ead₁₀₄, Ebc₁₀₈, where the strengths of the electric fields are the highest.

FIG. 8 shows a simplified top view of a memory device 800 according to alternative non-limiting embodiments. The memory device 800 is similar to the memory device 600, and thus, the common features are labelled with the same reference numerals and need not be discussed.

Similar to the memory device 600, in the memory device 800, the top edge Ead₁₀₄ of the bottom electrode 104 and the bottom edge Ebc₁₀₈ of the top electrode 108 may at least partially extend along different first and second vertical planes 604, 608. However, the top and bottom electrodes 108, 104 may be laterally offset from each other along both the X-axis and the Y-axis. In other words, referring to FIG. 8, the front surface 104 e of the bottom electrode 104 and the front surface 108 e of the top electrode 108 may at least partially extend along different third and fourth vertical planes 804, 808 respectively. These third and fourth vertical planes 804, 808 may be substantially parallel to each other and substantially perpendicular to the first and second vertical planes 604, 608. In addition, the third and fourth vertical planes 804, 808 may be laterally spaced apart from each other.

In the memory device 800, the top surface 104 a of the bottom electrode 104 may overlap with a corner Cbcf₁₀₈ of the top electrode 108, and the bottom surface 108 b of the top electrode 108 may overlap with a corner Cade₁₀₄ of the bottom electrode 104. In particular, the bottom surface 108 b of the top electrode 108 may partially overlap with the top surface 104 a of the bottom electrode 104 by a first overlap distance 810 parallel to the X-axis and by a second overlap distance 812 parallel to the Y-axis. Each of these overlap distances 810, 812 may be less than or equal to 50 nm, and may be less than or equal to 30 nm in some non-limiting embodiments. For example, each of these overlap distances 810, 812 may be about 10 nm, about 20 nm, or about 30 nm in a first, a second and a third non-limiting embodiment.

FIG. 9A shows a simplified perspective view of a memory device 900 according to alternative non-limiting embodiments. FIG. 9B shows a simplified top view of the memory device 900 and FIG. 9C shows a simplified cross-sectional view of the memory device 900 along the line C-C′ of FIG. 9B. The memory device 900 is similar to the memory device 100, and thus, the common features are labelled with the same reference numerals and need not be discussed.

As shown in FIGS. 9A to 9C, the top edge Ead₁₀₄ of the bottom electrode 104 and the bottom edge Ebc₁₀₈ of the top electrode 108 may at least partially extend along different first and second vertical planes 904, 908. These first and second vertical planes 904, 908 may be substantially parallel to and laterally spaced apart from each other. In particular, the entire bottom surface 108 b of the top electrode 108 may be spaced apart from the entire top surface 104 a of the bottom electrode 104 by a spacing 902 parallel to the X-axis as shown in FIG. 9A. The spacing 902 may be less than or equal to 30 nm. For example, the spacing 902 may be about 10 nm, about 20 nm, or about 30 nm in a first, a second and a third non-limiting embodiment. A distance D_(LR) parallel to the X-axis between the left surface 108 c of the top electrode 108 and the right surface 104 d of the bottom electrode 104 may be equal to the spacing 902, and may be smaller than a distance D_(LL) parallel to the X-axis between the left surfaces 108 c, 104 c of the top and bottom electrodes 108, 104 and a distance D_(RR) parallel to the X-axis between the right surfaces 108 d, 104 d of the top and bottom electrodes 108, 104.

Referring to FIGS. 9A and 9B, the top and bottom electrodes 108, 104 may be laterally offset along the X-axis but laterally aligned along the Y-axis. Accordingly, the front surface 104 e of the bottom electrode 104 and the front surface 108 e of the top electrode 108 may at least partially extend along a same third vertical plane 910 substantially perpendicular to the first and second vertical planes 904, 908.

Referring to FIG. 9C, when a sufficiently large potential difference is applied between the top and bottom electrodes 104, 108, conducting filaments 180 may be formed between the top and bottom electrodes 104, 108. The conducting filaments 180 may be confined between the top edge Ead₁₀₄ of the bottom electrode 104 and the bottom edge Ebc₁₀₈ of the top electrode 108, as the electric fields at these edges Ead₁₀₄, Ebc₁₀₈ may be higher than that at other parts of the memory device 900.

FIGS. 10A to 10C show simulated electric fields in memory devices 1000, 1002, 1004 when a sufficiently large potential difference is applied between the top and bottom electrodes 104, 108. For clarity of illustration, some reference numerals are omitted from FIGS. 10A to 10C. The memory devices 1000, 1002, 1004 may be similar to the memory device 900 but with different spacings 902 at 10 nm, 20 nm, or 30 nm, respectively. The simulated electric fields in FIGS. 10A to 10C were obtained with a thickness T₁₀₆ of each switching layer 106 set as 5 nm and a potential difference between the top and bottom electrodes 104, 108 set as 2V. The length of the conducting filaments (e.g. conducting filaments 180 as shown in FIG. 9C) may be determined as 11.2 nm, 20.6 nm and 30.4 nm respectively when the spacing 902 is 10 nm, 20 nm, or 30 nm. The minimum electric field strengths to form conducting filaments in the memory devices 1000, 1002, 1004 may similarly be determined using Equation (1) as approximately 1.79×10⁸V/m, 9.7×10⁷V/m and 6.58×10⁷V/m respectively.

As shown in FIGS. 10A to 10C, in each memory device 1000, 1002, 1004, the simulated electric field strength at the edge Ead₁₀₄ of the bottom electrode 104 and at the edge Ebc₁₀₈ of the top electrode 108 are higher than the simulated electric field strengths at other parts of the memory device 1000, 1002, 1004. In particular, the simulated electric field strength at the edge Ead₁₀₄ of the bottom electrode 104 is approximately 1.28×10⁸V/m, 7×10⁷V/m and 4.477×10⁷V/m in the memory device 1000, 1002, 1004 respectively; whereas, the simulated electric field strength at the edge Ebc₁₀₈ of the top electrode 108 is approximately 2.85×10⁸V/m, 1.73×10⁸V/m and 1.125×10⁸V/m in the memory device 1000, 1002, 1004 respectively. Accordingly, conducting filaments (e.g. conducting filaments 180 as shown in FIG. 9C) may be formed and confined between the edges Ead₁₀₄, Ebc₁₀₈ where the strengths of the electric fields are the highest.

FIG. 11 shows a simplified top view of a memory device 1100 according to alternative non-limiting embodiments. The memory device 1100 is similar to the memory device 900, and thus, the common features are labelled with the same reference numerals and need not be discussed.

Similar to the memory device 900, in the memory device 1100, the top edge Ead₁₀₄ of the bottom electrode 104 and the bottom edge Ebc₁₀₈ of the top electrode 108 may at least partially extend along different first and second vertical planes 904, 908. However, the top and bottom electrodes 108, 104 may be laterally offset from each other along both the X-axis and the Y-axis. In other words, referring to FIG. 11, the front surface 104 e of the bottom electrode 104 and the front surface 108 e of the top electrode 108 may at least partially extend along different third and fourth vertical planes 1104, 1108 respectively. These third and fourth vertical planes 1104, 1108 may be substantially parallel to each other and substantially perpendicular to the first and second vertical planes 904, 908. In addition, the third and fourth vertical planes 1104, 1108 may be laterally spaced apart from each other.

In particular, the bottom surface 108 b of the top electrode 108 may be spaced apart from the top surface 104 a of the bottom electrode 104 along both the X-axis and the Y-axis, by a first spacing 1110 parallel to the X-axis and a second spacing 1112 parallel to the Y-axis. Each of these spacings 1110, 1112 may be less than or equal to 30 nm. For example, each of these spacings 1110, 1112 may be about 10 nm, about 20 nm, or about 30 nm in a first, a second and a third non-limiting embodiment. The spacings 1110, 1112 may be substantially the same or may alternatively be different. A corner Cade₁₀₄ of the bottom electrode 104 may be nearer to the top electrode 108 as compared to the other corners of the bottom electrode 104, and a corner Cbcf₁₀₈ of the top electrode 108 may be nearer to the bottom electrode 104 as compared to the other corners of the top electrode 108. Accordingly, conducting filaments may be formed and confined between the corners Cade₁₀₄, Cbcf₁₀₈ of the bottom and top electrodes 104, 108.

In the memory devices 100, 400, 600, 800, 900, 1100, the top electrode 108 may be arranged on the right side of the bottom electrode 104 as seen from the top view. However, the top electrode 108 may alternatively be arranged in a similar manner relative to the bottom electrode 104, but on the left side of the bottom electrode 104 as seen from the top view. In these alternative non-limiting embodiments, a distance D_(RL) parallel to the X-axis between the right surface 108 d of the top electrode 108 and the left surface 104 c of the bottom electrode 104 may be smaller than or equal to a distance D_(RR) parallel to the X-axis between the right surfaces 108 d, 104 d of the top and bottom electrodes 108, 104 and a distance D_(LL) parallel to the X-axis between the left surfaces 108 c, 104 c of the top and bottom electrodes 108, 104.

FIG. 12A shows a simplified top view of a memory device 1200 according to alternative non-limiting embodiments. FIG. 12B shows a simplified cross-sectional view of the memory device 1200 along the line D-D′ of FIG. 12A. The memory device 1200 is similar to the memory device 800, and thus, the common features are labelled with the same reference numerals and need not be discussed.

Similar to the memory device 800, the top and bottom electrodes 108, 104 of the memory device 1200 may be laterally offset from each other along both the X-axis and the Y-axis. However, the top electrode 108 may be on the left side (instead of the right side) of the bottom electrode 104 as seen from the top view in FIG. 12A. Referring to FIG. 12B, a bottom edge Ebd₁₀₈ of the top electrode 108 and a top edge Eac₁₀₄ of the bottom electrode 104 may at least partially extend along different first and second vertical planes 1202, 1204 substantially parallel to and laterally spaced apart from each other. Referring to FIG. 12A, the front surface 108 e of the top electrode 108 and the front surface 104 e of the bottom electrode 104 may similarly at least partially extend along different third and fourth vertical planes 1206, 1208 laterally spaced apart from each other. The overlap distances 1210, 1212 along the X-axis and the Y-axis respectively may be similar to the distances 810, 812 in the memory device 800. As shown in FIG. 12A, the top surface 104 a of the bottom electrode 104 may overlap with a corner Cbde₁₀₈ of the top electrode 108 and the bottom surface 108 b of the top electrode 108 may overlap with a corner Cacf₁₀₄ of the bottom electrode 104. Conducting filaments may be formed and confined between these corners Cbde₁₀₈, Cacf₁₀₄ of the top and bottom electrodes 108, 104.

FIGS. 13A and 13B respectively show a perspective view and a top view of the memory device 1200 with simulated electric fields formed therein, when a sufficiently large potential difference is applied between the top and bottom electrodes 108, 104. For clarity of illustration, some reference numerals are omitted from FIGS. 13A and 13B.

As shown in FIGS. 13A and 13B, the simulated electric field strength at the corner Cbde₁₀₈ of the top electrode 108 is higher than the simulated electric field strengths at other parts of the top electrode 108. In particular, the simulated electric field strength at the corner Cbde₁₀₈ of the top electrode 108 is 3.57×10⁸V/m; whereas, the simulated electric field strengths at other corners Cbce₁₀₈, Cbcf₁₀₈ of the top electrode 108 are 3.366×10⁸V/m and 2.911×10⁸V/m respectively. Further, the simulated electric field strength at the corner Cacf₁₀₄ of the bottom electrode 104 is 2.409×10⁸ V/m. Therefore, conducting filaments may be formed and confined between the corners Cbde₁₀₈, Cacf₁₀₄ of the top and bottom electrodes 108, 104, as the electric fields at these corners Cbde₁₀₈, Cacf₁₀₄ may be the higher than that at other parts of the memory device 1200.

As shown in FIG. 1A to FIG. 13, the bottom surface 108 b of the top electrode 108 and the top surface 104 a of the bottom electrode 104 of each memory device 100-1200 may have a same shape. However, the bottom surface 108 b of the top electrode 108 and the top surface 104 a of the bottom electrode 104 may alternatively have different shapes.

FIG. 14A shows a simplified top view of a memory device 1400 according to alternative non-limiting embodiments and FIG. 14B shows a simplified cross-sectional view of the memory device 1400 along the line E-E′ of FIG. 14A. The memory device 1400 is similar to the memory device 800, and thus, the common features are labelled with the same reference numerals and need not be discussed.

As shown in FIG. 14A, in the memory device 1400, the bottom surface 108 b of the top electrode 108 and the top surface 104 a of the bottom electrode 104 may have different shapes. In particular, while the top electrode 108 may be a cuboid with surfaces 108 a-108 f, the bottom electrode 104 may include a first segment 104 s 1 and a second segment 104 s 2 substantially perpendicular to each other. In other words, the bottom electrode 104 may have L-shaped top and bottom surfaces 104 a, 104 b. The bottom electrode 104 may further include a left surface 104 c, a first right surface 104 d 1, a second right surface 104 d 2, a front surface 104 e, a first back surface 104 f 1 and a second back surface 104 f 2. The first right surface 104 d 1 may be further right than the second right surface 104 d 2, and the second back surface 104 f 2 may be further back than the first back surface 104 f 1.

As shown in FIGS. 14A and 14B, the bottom surface 108 b of the top electrode 108 may partially overlap with the top surface 104 a of the bottom electrode 104, with the front surface 104 e of the bottom electrode 104 and the front surface 108 e of the top electrode 108 extending along different vertical planes 1402, 1404. The bottom surface 108 b of the top electrode 108 may overlap with a corner Cad2 f 1 ₁₀₄ of the bottom electrode 104, where this corner Cad2 f 1 ₁₀₄ may lie between the first segment 104 s 1 and the second segment 104 s 2 of the bottom electrode 104. The top surface 104 a of the bottom electrode 104 may overlap with multiple corners Cbce₁₀₈, Cbcf₁₀₈, Cbde₁₀₈ of the top electrode 108, among which the corner Cbce₁₀₈ may be nearest to the corner Cad2 f 1 ₁₀₄ of the bottom electrode 104. Accordingly, when a sufficiently large potential difference is applied between the top and bottom electrodes 104, 108 of the memory device 1400, electric field strengths at the corners Cad2 f 1 ₁₀₄, Cbce₁₀₈ may be higher than at other parts of the memory device 1400 and thus, conducting filaments 180 may be formed between the corners Cad2 f 1 ₁₀₄, Cbce₁₀₈ of the respective electrodes 104, 108.

The overlap area A₁₄₀₀ between the bottom surface 108 b of the top electrode 108 and the top surface 104 a of the bottom electrode 104 in the memory device 1400 may be greater than the overlap area A₈₀₀ between the bottom surface 108 b of the top electrode 108 and the top surface 104 a of the bottom electrode 104 in the memory device 800. This may provide a greater localized electric field between the top and bottom electrodes 108, 104 in the memory device 1400, hence allowing stronger conducting filaments 180 to be formed between the electrodes 108, 104. For example, a ratio of the overlap area A₁₄₀₀ to the overlap area A₈₀₀ may range from about two to about four, and may in one non-limiting embodiment, be about three. In various non-limiting embodiments, the overlap area A₈₀₀ may range from about 25 nm² to about 400 nm²; whereas, the overlap area A₁₄₀₀ may range from about 75 nm² to about 1200 nm².

In the memory device 1400, the top electrode 108 may be sized and positioned such that the left surface 104 c of the bottom electrode 104 and the left surface 108 c of the top electrode 108 may at least partially extend along different vertical planes 1406, 1408, and the right surface 108 d of the top electrode 108 and the first right surface 104 d 1 of the bottom electrode 104 may at least partially extend along different vertical planes 1410, 1412. The vertical planes 1406, 1408, 1410, 1412 may be substantially parallel to and laterally spaced apart from one another. However, the top electrode 108 may alternatively be sized and positioned differently.

FIG. 15 shows a simplified top view of a memory device 1500 according to alternative non-limiting embodiments. The memory device 1500 is similar to the memory device 1400, and thus, the common features are labelled with the same reference numerals and need not be discussed.

As shown in FIG. 15, in the memory device 1500, the top electrode 108 may be sized and positioned relative to the bottom electrode 104, such that the left surface 108 c of the top electrode 108 and the left surface 104 c of the bottom electrode 104 may at least partially extend along a same vertical plane 1502. Similar to the memory device 1400, the top surface 104 a of the bottom electrode 104 may overlap with multiple corners Cbce₁₀₈, Cbcf₁₀₈, Cbde₁₀₈ of the top electrode 108, and the bottom surface 108 b of the top electrode 108 may overlap with a corner Cad2 f 1 ₁₀₄ of the bottom electrode 104. However, in the memory device 1500, the corner Cbde₁₀₈ (instead of the corner Cbce₁₀₈) of the top electrode 108 may be nearest to the corner Cad2 f 1 ₁₀₄ of the bottom electrode 104. Accordingly, when a sufficiently large potential difference is applied between the electrodes 104, 108 of the memory device 1500, conducting filaments may be formed between the corner Cbde₁₀₈ of the top electrode 108 and the corner Cad2 f 1 ₁₀₄ of the bottom electrode 104.

FIG. 16 shows a simplified top view of a memory device 1600 according to alternative non-limiting embodiments. The memory device 1600 is similar to the memory device 1400, and thus, the common features are labelled with the same reference numerals and need not be discussed.

As shown in FIG. 16, in the memory device 1600, the top electrode 108 may be sized and positioned relative to the bottom electrode 104, such that the right surface 108 d of the top electrode 108 and the first right surface 104 d 1 of the bottom electrode 104 may extend at least partially along a same vertical plane 1602. Similar to the memory device 1400, the top surface 104 a of the bottom electrode 104 may overlap with multiple corners Cbce₁₀₈, Cbcf₁₀₈, Cbde₁₀₈ of the top electrode 108, and the bottom surface 108 b of the top electrode 108 may overlap with a corner Cad2 f 1 ₁₀₄ of the bottom electrode 104. The corner Cbce₁₀₈ of the top electrode 108 may similarly be nearest to the corner Cad2 f 1 ₁₀₄ of the bottom electrode 104. Accordingly, when a sufficiently large potential difference is applied between the electrodes 104, 108 of the memory device 1600, conducting filaments may be formed between the corner Cbce₁₀₈ of the top electrode 108 and the corner Cad2 f 1 ₁₀₄ of the bottom electrode 104.

FIG. 17 shows a simplified top view of a memory device 1700 according to alternative non-limiting embodiments. The memory device 1700 is similar to the memory device 1400, and thus, the common features are labelled with the same reference numerals and need not be discussed.

As compared to the memory device 1400, in the memory device 1700, the bottom electrode 104 may not only include a first segment 104 s 1 and a second segment 104 s 2 substantially perpendicular to each other, but may also include a third segment 104 s 3 substantially perpendicular to the second segment 104 s 2 and substantially parallel to the first segment 104 s 1. In particular, the top and bottom surfaces 104 a, 104 b of the bottom electrode 104 may be U-shaped instead of L-shaped. The bottom electrode 104 of the memory device 1700 may also include a front surface 104 e, first, second and third back surfaces 104 f 1, 104 f 2, 104 f 3, first and second left surfaces 104 c 1, 104 c 2, and first and second right surfaces 104 d 1, 104 d 2. The second and third back surfaces 104 f 2, 104 f 3 may be laterally aligned and may be further back as compared to the first back surface 104 f 1. Further, the first left surface 104 c 1 may be further left than the second left surface 104 c 2, and the first right surface 104 d 1 may be further right than the second right surface 104 d 2. As shown in FIG. 17, the bottom surface 108 b of the top electrode 108 may similarly overlap with a corner Cad2 f 1 ₁₀₄ of the bottom electrode 104; and the top surface 104 a of the bottom electrode 104 may similarly overlap with multiple corners Cbcf₁₀₈, Cbce₁₀₈, Cbde₁₀₈ of the top electrode 108, among which the corner Cbce₁₀₈ of the top electrode 108 may be nearest to the corner Cad2 f 1 ₁₀₄ of the bottom electrode 104.

FIGS. 18A and 18B respectively show a perspective view and a top view of the memory device 1700 with simulated electric fields formed therein, when a sufficiently large potential difference is applied between the electrodes 104, 108. For clarity of illustration, some reference numerals are omitted from FIGS. 18A and 18B.

As shown in FIGS. 18A and 18B, the simulated electric field strength at the corner Cbce₁₀₈ of the top electrode 108 is higher than that at other parts of the top electrode 108. In particular, the simulated electric field strength at the corner Cbce₁₀₈ of the top electrode 108 is 4.542×10⁸ V/m; whereas, the simulated electric field strengths at the corner Cbcf₁₀₈ and the corner Cbde₁₀₈ are 4.111×10⁸ V/m and 3.549×10⁸ V/m respectively. Further, the simulated electric field strength at the corner Cad2 f 1 ₁₀₄ of the bottom electrode 104 is 1.982×10⁸ V/m. Therefore, conducting filaments may be formed between the corner Cbce₁₀₈ of the top electrode 108 and the corner Cad2 f 1 ₁₀₄ of the bottom electrode 104, where the electric field strengths may be the highest.

FIG. 19 shows a simplified top view of a memory device 1900 according to alternative non-limiting embodiments. The memory device 1900 is similar to the memory device 1400, and thus, the common features are labelled with the same reference numerals and need not be discussed.

As shown in FIG. 19, the top electrode 108 of the memory device 1900 may have a same shape as the top electrode 108 of the memory device 1400, and the bottom electrode 104 of the memory device 1900 may have a same shape as the bottom electrode 104 of the memory device 1400. However, the bottom surface 108 b of the top electrode 108 may be spaced apart from the top surface 104 a of the bottom electrode 104 along both the X-axis and the Y-axis, by a first spacing 1910 parallel to the X-axis and a second spacing 1912 parallel to the Y-axis (similar to the memory device 1100 as described above). Each of these spacings 1910, 1912 may be less than or equal to 30 nm. Further, these spacings 1910, 1912 may be substantially the same as each other or may alternatively be different from each other. A corner Cbce₁₀₈ of the top electrode 108 may be nearer to the bottom electrode 104 as compared to the other corners of the top electrode 108. A corner Cad2 f 1 ₁₀₄ lying between the first segment 104 s 1 and the second segment 104 s 2 of the bottom electrode 104 may be nearer to the corner Cbce₁₀₈ of the top electrode 108, as compared to the other corners of the bottom electrode 104. Accordingly, when a sufficiently large potential difference is applied between the electrodes 104, 108 of the memory device 1900, electric field strengths at the corners Cad2 f 1 ₁₀₄, Cbce₁₀₈ may be higher than at other parts of the memory device 1900 and thus, conducting filaments may be formed between the corners Cad2 f 1 ₁₀₄, Cbce₁₀₈ of the respective electrodes 104, 108.

In each of the memory devices 100-1900 described above, the top electrode 108 is depicted as a cuboid having surfaces 108 a-108 f However, the top electrode 108 may be in a different shape. Similarly, the bottom electrode 104 may also be differently shaped from those in the memory devices 100-1900. For example, the bottom electrode 104 of the memory device 1900 may instead be of a same shape as the bottom electrode 104 of the memory device 1700. For example, the bottom electrode 104 of the memory device 400 may instead be of a same shape as the bottom electrode 104 of the memory device 1900, and the corners Cad2 f 1 ₁₀₄, Cbce₁₀₈ may be aligned along a same vertical axis. Further, in FIGS. 1A-19, the electrodes 104, 108 are depicted with their surfaces entirely parallel to the X or Y axis. For example, the surface 108 c of the memory device 100 is depicted as entirely parallel to the X axis and hence, entirely extending along the plane 158. However, the electrodes 104, 108 may instead have rounded edges or corners. For example, the surface 108 c of the memory device 100 may have rounded edges and hence, may be only partially extending along the plane 158. This may be due to the limitations in the fabrication of the electrodes 104, 108, although, certain techniques may be implemented to increase the sharpness of the edges and corners of the electrodes 104, 108, so as to improve filament confinement. For example, using serifs on the photoresist masks for forming the electrodes 104, 108 may increase the sharpness of the edges and corners (e.g. from a 5.2 nm corner pullback to a 2.9 nm corner pullback).

As described above, the memory devices 100-1900 may include a single bottom electrode 104 and a single top electrode 108. These memory devices 100-1900 may be referred to as one transistor one resistor (1T1R) devices. In alternative non-limiting embodiments, the memory device may include at least one additional top electrode arranged over the switching layer 106 in a laterally offset position relative to the bottom electrode 104. These memory devices may be referred to as one transistor N resistors (1TNR) memory devices, where N may be the total number of top electrodes. In these memory devices, each of the at least one additional top electrode may be substantially planar. Further, for each of the at least one additional top electrode, at most a part of a bottom surface of the additional top electrode may overlap the top surface 104 a of the bottom electrode 104, and at most a part of the top surface 104 a of the bottom electrode 104 may overlap the bottom surface of the additional top electrode. Each additional top electrode may be arranged relative to the bottom electrode 104 in a manner similar to the arrangement between the top electrode 108 and the bottom electrode 104 in any of the above-described memory devices 100-1900. Within a same memory device, the arrangement between each top electrode and the bottom electrode 104 may be the same as or different from that of another top electrode and the bottom electrode 104. Further, the top and bottom electrodes of the memory device may be of any shape, and the electrodes within a same memory device may have the same shapes or different shapes.

FIG. 20A shows a simplified perspective view of a memory device 2000 according to alternative non-limiting embodiments. FIG. 20B shows a simplified top view of the memory device 2000 and FIG. 20C shows a simplified cross-sectional view of the memory device 2000 along the line F-F′ of FIG. 20B. The memory device 2000 may be a 1T2R memory device.

As shown in FIGS. 20A to 20C, the memory device 2000 may include a first substantially planar top electrode 1081 and a second substantially planar top electrode 1082. Each top electrode 1081, 1082 may include surfaces 1081 a-1081 f, 1082 a-1082 f similar to those of the top electrode 108 of the memory device 100 as described above. The dimensions W₁₀₈₁, L₁₀₈₁, T₁₀₈₁, W₁₀₈₂, L₁₀₈₂, T₁₀₈₂ of the top electrodes 1081, 1082 of the memory device 2000 may also be similar to those of the top electrode 108 of the memory device 100. As shown in FIGS. 20A to 20C, the first and second top electrodes 1081, 1082 may be arranged relative to the bottom electrode 104 in a manner similar to the arrangement between the top electrode 108 and the bottom electrode 104 of the memory device 100. In particular, the edge Ebc₁₀₈₁ of the first top electrode 1081 and the edge Ead₁₀₄ of the bottom electrode 104 may at least partially extend along a same first vertical plane 2008; whereas, the edge Ebd₁₀₈₂ of the second top electrode 1082 and the edge Eac₁₀₄ of the bottom electrode 104 may at least partially extend along a same second vertical plane 2009 substantially parallel to and laterally spaced apart from the first vertical plane 2008. A distance D_(LR1) between the left surface 1081 c of the first top electrode 1081 and the right surface 104 d of the bottom electrode 104 may be smaller than a distance D_(LL1) between the left surfaces 1081 c, 104 c of the first top electrode 1081 and the bottom electrode 104, and a distance D_(RR1) between the right surfaces 1081 d, 104 d of the first top electrode 1081 and the bottom electrode 104. Similarly, a distance D_(RL2) between the right surface 1082 d of the second top electrode 1082 and the left surface 104 c of the bottom electrode 104 may be smaller than a distance D_(RR2) between the right surfaces 1082 d, 104 d of the second top electrode 1082 and the bottom electrode 104, and a distance D_(LL2) between the left surfaces 1082 c, 104 c of the second top electrode 1082 and the bottom electrode 104. The distances D_(LR1), D_(LL1), D_(RR1), D_(RL2), D_(LL2), D_(RR2) are parallel to the X-axis.

As shown in FIG. 20C, upon application of a sufficiently large potential difference between the first top electrode 1081 and the bottom electrode 104 of the memory device 2000, first conducting filaments 181 may be formed between these electrodes 104, 1081; whereas, upon application of a sufficiently large potential difference between the second top electrode 1082 and the bottom electrode 104 of the memory device 2000, second conducting filaments 182 may be formed between these electrodes 104, 1082. The first conducting filaments 181 may be formed and confined between the edge Ead₁₀₄ of the bottom electrode 104 and the edge Ebc₁₀₈₁ of the first top electrode 1081. Similarly, the second conducting filaments 182 may be formed and confined between the edge Eac₁₀₄ of the bottom electrode 104 and the edge Ebd₁₀₈₂ of the second top electrode 1082.

FIG. 21 shows simulated electric fields formed in the memory device 2000 when sufficiently large potential differences are applied between the first top electrode 1081 and the bottom electrode 104, and between the second top electrode 1082 and the bottom electrode 104. For clarity of illustration, some reference numerals are omitted from FIG. 21. As shown in FIG. 21, the electric field strengths at the edge Ead₁₀₄ of the bottom electrode 104, at the edge Ebc₁₀₈₁ of the first top electrode 1081, at the edge Eac₁₀₄ of the bottom electrode 104, and at the edge Ebd₁₀₈₂ of the second top electrode 1082 are higher than the electric field strengths at other parts of the memory device 2000. Accordingly, formation of the conducting filaments (e.g. conducting filaments 181, 182 of FIG. 20C) may be confined between the edges Ebc₁₀₈₁, Ead₁₀₄ and between the edges Ebd₁₀₈₂, Eac₁₀₄ where the strengths of the electric fields are the highest.

FIG. 22 shows a simplified top view of a memory device 2200 according to alternative non-limiting embodiments. The memory device 2200 is similar to the memory device 2000, and thus, the common features are labelled with the same reference numerals and need not be discussed. The memory device 2200 may be a 1T2R memory device.

In the memory device 2200, the arrangement between each top electrode 1081, 1082 and the bottom electrode 104 may be similar to the arrangement between the top electrodes 108 and the bottom electrodes 104 of the memory devices 800, 1200. In particular, the top surface 104 a of the bottom electrode 104 may partially overlap with both the bottom surfaces 1081 b, 1082 b of the top electrodes 1081, 1082, such that it may overlap with a corner Cbce₁₀₈₁ of the first top electrode 1081 and with a corner Cbde₁₀₈₂ of the second top electrode 1082. The bottom surface 1081 b of the first top electrode 1081 may overlap with a first corner Cadf₁₀₄ of the bottom electrode 104; whereas the bottom surface 1082 b of the second top electrode 1082 may overlap with a second corner Cacf₁₀₄ of the bottom electrode 104. When a sufficiently large potential difference is applied between the first top electrode 1081 and the bottom electrode 104, conducting filaments may be formed and confined between the corners Cadf₁₀₄, Cbce₁₀₈₁ of the respective electrodes 104, 1081. Similarly, when a sufficiently large potential difference is applied between the second top electrode 1082 and the bottom electrode 104, conducting filaments may be formed and confined between the corners Cacf₁₀₄, Cbde₁₀₈₂ of the respective electrodes 104, 1082.

FIG. 23 shows a simplified top view of a memory device 2300 according to alternative non-limiting embodiments. The memory device 2300 is similar to the memory device 2200, and thus, the common features are labelled with the same reference numerals and need not be discussed. The memory device 2300 may be a 1T2R memory device.

As compared to the memory device 2200, the bottom electrode 104 in the memory device 2300 may be of a different shape. In particular, the bottom electrode 104 of the memory device 2300 may be similar in shape as that in the memory device 1700, with similar first to third segments 104 s 1, 104 s 2, 104 s 3, and surfaces including a front surface 104 e, first, second and third back surfaces 104 f 1, 104 f 2, 104 f 3, first and second left surfaces 104 c 1, 104 c 2, and first and second right surfaces 104 d 1, 104 d 2.

In the memory device 2300, the bottom surface 1081 b of the first top electrode 1081 may overlap with a first corner Cac2 f 1 ₁₀₄ of the bottom electrode 104 and the bottom surface 1082 b of the second top electrode 1082 may overlap with a second corner Cad2 f 1 ₁₀₄ of the bottom electrode 104. The first corner Cac2 f 1 ₁₀₄ of the bottom electrode 104 may lie between the second and third segments 104 s 2, 104 s 3, and the second corner Cad2 f 1 ₁₀₄ of the bottom electrode 104 may lie between the first and second segments 104 s 1, 104 s 2. In addition, the top surface 104 a of the bottom electrode 104 may overlap with multiple corners Cbdf₁₀₈₁, Cbde₁₀₈₁, Cbce₁₀₈₁ of the first top electrode 1081, among which the corner Cbde₁₀₈₁ may be nearest to the first corner Cac2 f 1 ₁₀₄ of the bottom electrode 104. Similarly, the top surface 104 a of the bottom electrode 104 may also overlap with multiple corners Cbcf₁₀₈₂, Cbce₁₀₈₂, Cbde₁₀₈₂ of the second top electrode 1082, among which the corner Cbce₁₀₈₂ may be nearest to the second corner Cad2 f 1 ₁₀₄ of the bottom electrode 104.

Accordingly, when a sufficiently large potential difference is applied between the first top electrode 1081 and the bottom electrode 104, conducting filaments may be formed and confined between the corners Cbde₁₀₈₁, Cac2 f 1 ₁₀₄ of the respective electrodes 1081, 104. Similarly, when a sufficiently large potential difference is applied between the second top electrode 1082 and the bottom electrode 104, conducting filaments may be formed and confined between the corners Cbce₁₀₈₂, Cad2 f 1 ₁₀₄ of the respective electrodes 1082, 104. As compared to the overlap area A₂₂₀₀₁, A₂₂₀₀₂ between each top electrode 1081, 1082 and the bottom electrode 104 in the memory device 2200, the overlap area A₂₃₀₀₁, A₂₃₀₀₂ between each top electrode 1081, 1082 and the bottom electrode 104 in the memory device 2300 may be greater. Hence, the electric field strengths between the corners Cbde₁₀₈₁, Cac2 f 1 ₁₀₄, and between the corners Cbce₁₀₈₂, Cad2 f 1 ₁₀₄ may be higher and in turn, stronger conducting filaments may be formed between the bottom electrode 104 and each top electrode 1081, 1082.

FIGS. 24A and 24B respectively show a perspective view and a top view of the memory device 2300 with simulated electric fields formed therein, when a sufficiently large potential difference is applied between the first top electrode 1081 and the bottom electrode 104, and between the second top electrode 1082 and the bottom electrode 104. For clarity of illustration, some reference numerals are omitted from FIGS. 24A and 24B.

As shown in FIGS. 24A and 24B, the electric field strengths at the corner Cbde₁₀₈₁ of the first top electrode 1081 may be higher than that at other parts of the first top electrode 1081. Similarly, the electric field strength at the corner Cbce₁₀₈₂ of the second top electrode 1082 may be higher than that at other parts of the second top electrode 1082. Therefore, conducting filaments may be formed and confined between the corner Cbde₁₀₈₁ of the first top electrode 1081 and the first corner Cac2 f 1 ₁₀₄ of the bottom electrode 104, and between the corner Cbce₁₀₈₂ of the second top electrode 1082 and the second corner Cad2 f 1 ₁₀₄ of the bottom electrode 104.

FIG. 25 shows a simplified top view of a memory device 2500 according to alternative non-limiting embodiments. The memory device 2500 is similar to the memory device 2200, and thus, the common features are labelled with the same reference numerals and need not be discussed. The memory device 2500 may be a 1T2R memory device.

As compared to the memory device 2200, the bottom electrode 104 in the memory device 2500 may be of a different shape. In particular, the bottom electrode 104 may include a first segment 104 s 1 and a second segment 104 s 2 substantially perpendicular to and approximately in the middle of the first segment 104 s 1. In other words, the bottom electrode 104 may have T-shaped top and bottom surfaces 104 a, 104 b. As shown in FIG. 25, the bottom electrode 104 may also include a front surface 104 e, first and second left surfaces 104 c 1, 104 c 2, first and second right surfaces 104 d 1, 104 d 2 and first, second and third back surfaces 104 f 1, 104 f 2, 104 f 3.

As shown in FIG. 25, the bottom surface 1081 b of the first top electrode 1081 may overlap with a first corner Cad2 f 3 ₁₀₄ of the bottom electrode 104, and the bottom surface 1082 b of the second top electrode 1082 may overlap with a second corner Cac2 f 2 ₁₀₄ of the bottom electrode 104. The first and second corners Cad2 f 3 ₁₀₄, Cac2 f 2 ₁₀₄ of the bottom electrode 104 may both lie between the first and second segments 104 s 1, 104 s 2 but on opposite sides of the second segment 104 s 2. The top surface 104 a of the bottom electrode 104 may overlap with multiple corners Cbcf₁₀₈₁, Cbce₁₀₈₁, Cbde₁₀₈₁ of the first top electrode 1081, among which the corner Cbce₁₀₈₁ may be nearest to the first corner Cad2 f 3 ₁₀₄ of the bottom electrode 104. The top surface 104 a of the bottom electrode 104 may also overlap with multiple corners Cbdf₁₀₈₂, Cbde₁₀₈₂, Cbce₁₀₈₂ of the second top electrode 1082, among which the corner Cbde₁₀₈₂ may be nearest to the second corner Cac2 f 2 ₁₀₄ of the bottom electrode 104.

Accordingly, when a sufficiently large potential difference is applied between the first top electrode 1081 and the bottom electrode 104, conducting filaments may be formed and confined between the corners Cbce₁₀₈₁, Cad2 f 3 ₁₀₄ of the respective electrodes 1081, 104. Similarly, when a sufficiently large potential difference is applied between the second top electrode 1082 and the bottom electrode 104, conducting filaments may be formed and confined between the corners Cbde₁₀₈₂, Cac2 f 2 ₁₀₄ of the respective electrodes 1082, 104. As compared to the overlap area A₂₂₀₀₁, A₂₂₀₀₂ between each top electrode 1081, 1082 and the bottom electrode 104 in the memory device 2200, the overlap area A₂₅₀₀₁, A₂₅₀₀₂ between each top electrode 1081, 1082 and the bottom electrode 104 in the memory device 2500 may be greater. Hence, the electric field strengths between the corners Cbce₁₀₈₁, Cad2 f 3 ₁₀₄, and between the corners Cbde₁₀₈₂, Cac2 f 2 ₁₀₄ may be higher and in turn, stronger conducting filaments may be formed between the bottom electrode 104 and each top electrode 1081, 1082.

FIGS. 26A and 26B respectively show a perspective view and a top view of the memory device 2500 with simulated electric fields formed therein, when a sufficiently large potential difference is applied between the first top electrode 1081 and the bottom electrode 104, and between the second top electrode 1082 and the bottom electrode 104. For clarity of illustration, some reference numerals are omitted from FIGS. 26A and 26B.

As shown in FIGS. 26A and 26B, the electric field strengths at the corner Cbce₁₀₈₁ of the first top electrode 1081 may be higher than that at other parts of the first top electrode 1081. Similarly, the electric field strength at the corner Cbde₁₀₈₂ of the second top electrode 1082 may be higher than that at other parts of the second top electrode 1082. Therefore, conducting filaments may be formed and confined between the corner Cbce₁₀₈₁ of the first top electrode 1081 and the first corner Cad2 f 3 ₁₀₄ of the bottom electrode 104, and between the corner Cbde₁₀₈₂ of the second top electrode 1082 and the second corner Cac2 f 2 ₁₀₄ of the bottom electrode 104.

FIGS. 27 and 28 respectively show simplified top views of a memory device 2700 and a memory device 2800 according to alternative non-limiting embodiments. The memory devices 2700, 2800 may be 1T3R memory devices.

As shown in FIGS. 27 and 28, each memory device 2700, 2800 may include a bottom electrode 104 having a first segment 104 s 1 and a second segment 104 s 2 substantially perpendicular to each other. Accordingly, the bottom electrode 104 of each memory device 2700, 2800 may have L-shaped top and bottom surfaces 104 a, 104 b. However, the bottom electrodes 104 of the memory devices 2700, 2800 may be oriented differently. Therefore, while the bottom electrode 104 of the memory device 2700 may include first and second front surfaces 104 e 1, 104 e 2, first and second left surfaces 104 c 1, 104 c 2, a right surface 104 d and a back surface 104 f, the bottom electrode 104 of the memory device 2800 may include a front surface 104 e, a left surface 104 c, first and second right surfaces 104 d 1, 104 d 2, and first and second back surfaces 104 f 1, 104 f 2.

Referring to FIGS. 27 and 28, each memory device 2700, 2800 may further include three top electrodes including first, second and third top electrodes 1081, 1082, 1083. In each memory device 2700, 2800, the top surface 104 a of the bottom electrode 104 may overlap with a corner of each of the top electrodes 1081, 1082, 1083. In particular, in the memory device 2700, the top surface 104 a of the bottom electrode 104 may overlap with corners Cbde₁₀₈₁, Cbce₁₀₈₂ and Cbcf₁₀₈₃ of the first, second and third top electrodes 1081, 1082, 1083, respectively; whereas, in the memory device 2800, the top surface 104 a of the bottom electrode 104 may overlap with corners Cbde₁₀₈₁, Cbcf₁₀₈₂ and Cbdf₁₀₈₃ of the first, second and third top electrodes 1081, 1082, 1083, respectively. Further, the bottom surface 1081 b, 1082 b, 1083 b of each top electrode 1081, 1082, 1083 may overlap with a corner of the bottom electrode 104. In particular, in the memory device 2700, the bottom surfaces 1081 b, 1082 b, 1083 b of the first, second and third top electrodes 1081, 1082, 1083 may overlap with the corners Cac1 f ₁₀₄, Cadf₁₀₄ and Cade1 ₁₀₄ of the bottom electrode 104, respectively. Whereas, in the memory device 2800, the bottom surfaces 1081 b, 1082 b, 1083 b of the first, second and third top electrodes 1081, 1082, 1083 may overlap with the corners Cacf2 ₁₀₄, Cad1 e ₁₀₄ and Cace₁₀₄ of the bottom electrode 104, respectively.

In each memory device 2700, 2800, when a sufficiently large potential difference is applied between one of the top electrodes 1081/1082/1083 and the bottom electrode 104, conducting filaments may be formed and confined between the corner of the top electrode 1081/1082/1083 overlapping the top surface 104 a of the bottom electrode 104, and the corner of the bottom electrode 104 overlapping the bottom surface 1081 b/1082 b/1083 b of the top electrode 1081/1082/1083. For example, in the memory device 2700, conducting filaments may be formed and confined between the corners Cbde₁₀₈₁ and Cac1 f ₁₀₄, the corners Cbce₁₀₈₂ and Cadf₁₀₄, and/or the corners Cbcf₁₀₈₃ and Cade1 ₁₀₄; whereas, in the memory device 2800, conducting filaments may be formed and confined between the corners Cbde₁₀₈₁ and Cacf2 ₁₀₄, the corners Cbcf₁₀₈₂ and Cad1 e ₁₀₄, and the corners Cbdf₁₀₈₃ and Cace₁₀₄.

FIGS. 29, 31, 32 and 34 respectively show simplified top views of memory devices 2900, 3100, 3200, 3400 according to alternative non-limiting embodiments. FIGS. 30A and 30B respectively show a perspective view and a top view of the memory device 2900 with simulated electric fields formed therein. FIGS. 33A and 33B respectively show a perspective view and a top view of the memory device 3200 with simulated electric fields formed therein. FIGS. 35A and 35B respectively show a perspective view and a top view of the memory device 3400 with simulated electric fields formed therein. The memory devices 2900, 3100, 3200, 3400 may be 1T4R memory devices.

As shown in FIGS. 29-34, the memory devices 2900, 3100, 3200, 3400 may be similar to one another. In particular, each memory device 2900, 3100, 3200, 3400 may include a single bottom electrode 104 and four top electrodes including a first top electrode 1081, a second top electrode 1082, a third top electrode 1083 and a fourth top electrode 1084. The top electrodes 1081-1084 of each memory device 2900, 3100, 3200, 3400 may each be a cuboid having surfaces 1081 a-1081 f, 1082 a-1082 f, 1083 a-1083 f and 1084 a-1084 f similar to the top electrode 108 of the memory device 100.

Comparing the memory device 2900 with the memory device 3100, the bottom electrode 104 of each of these memory devices 2900, 3100 may also be a cuboid having surfaces 104 a-104 f, where the bottom electrode 104 may be larger than each top electrode 1081-1084. However, the relative arrangement between the top electrodes 1081-1084 and the bottom electrode 104 in the memory device 2900 may be different from that in the memory device 3100.

In particular, referring to FIG. 29, in the memory device 2900, each top electrode 1081-1084 may be arranged relative to the bottom electrode 104 in a manner similar to that in the memory device 400. Accordingly, the corners Cbde₁₀₈₁, Cbce₁₀₈₂, Cbcf₁₀₈₃, Cbdf₁₀₈₄ of the first, second, third and fourth top electrodes 1081-1084 may be vertically aligned with the corners Cacf₁₀₄, Cadf₁₀₄, Cade₁₀₄, Cace₁₀₄ of the bottom electrode 104. As shown in FIGS. 30A and 30B, the electric field strengths between the corners Cbde₁₀₈₁, Cbce₁₀₈₂, Cbcf₁₀₈₃, Cbdf₁₀₈₄ of the top electrodes 1081-1084 and the respective vertically aligned corners Cacf₁₀₄, Cadf₁₀₄, Cade₁₀₄, Cace₁₀₄ of the bottom electrode 104 may be higher than that at other parts of the memory device 2900. Conducting filaments may thus be formed and confined between the corners Cbde₁₀₈₁, Cbce₁₀₈₂, Cbcf₁₀₈₃, Cbdf₁₀₈₄ of the top electrodes 1081-1084 and the corners Cacf₁₀₄, Cadf₁₀₄, Cade₁₀₄, Cace₁₀₄ of the bottom electrode 104, respectively.

On the other hand, referring to FIG. 31, in the memory device 3100, each top electrode 1081-1084 may be arranged relative to the bottom electrode 104 in a manner similar to that in the memory device 800. Accordingly, the top surface 104 a of the bottom electrode 104 may overlap with a corner Cbde₁₀₈₁ of the first top electrode 1081, a corner Cbce₁₀₈₂ of the second top electrode 1082, a corner Cbcf₁₀₈₃ of the third top electrode 1083 and a corner Cbdf₁₀₈₄ of the fourth top electrode 1084. The bottom surfaces 1081 b, 1082 b, 1083 b, 1084 b of the first, second, third and fourth top electrodes 1081-1084 may overlap with corners Cacf₁₀₄, Cadf₁₀₄, Cade₁₀₄ and Cace₁₀₄ of the bottom electrode 104, respectively. Conducting filaments may thus be formed and confined between the corners Cbde₁₀₈₁, Cbce₁₀₈₂, Cbcf₁₀₈₃, Cbdf₁₀₈₄ of the top electrodes 1081-1084 and the corners Cacf₁₀₄, Cadf₁₀₄, Cade₁₀₄ and Cace₁₀₄ of the bottom electrode 104, respectively.

Similar to the memory device 3100, in the memory devices 3200, 3400, the bottom surfaces 1081 b-1084 b of each top electrode 1081-1084 may partially overlap with the top surface 104 a of the bottom electrode 104. However, the bottom electrodes 104 of the memory devices 3200, 3400 may have a different shape as compared to the bottom electrode 104 of the memory device 3100.

In particular, referring to FIG. 32, the memory device 3200 may include a bottom electrode 104 having H-shaped top and bottom surfaces 104 a, 104 b. In other words, the bottom electrode 104 may include a first segment 104 s 1, a second segment 104 s 2 and a third segment 104 s 3, where the first and third segments 104 s 1, 104 s 3 may extend substantially parallel to each other and the second segment 104 s 2 may extend substantially perpendicular to the first and third segments 104 s 1, 104 s 3 between these segments 104 s 1, 104 s 3. The bottom electrode 104 may thus further include a left surface 104 c, a right surface 104 d, first, second and third front surfaces 104 e 1, 104 e 2, 104 e 3, and first, second and third back surfaces 104 f 1, 104 f 2, 104 f 3. The bottom surfaces 1081 b, 1084 b of the first and fourth top electrodes 1081, 1084 may overlap with corners Cad2 f 1 ₁₀₄ and Cad3 e 1 ₁₀₄ of the bottom electrode 104 respectively, where these corners Cad2 f 1 ₁₀₄, Cad3 e 1 ₁₀₄ may lie between the first and second segments 104 s 1, 104 s 2 of the bottom electrode 104. Further, the bottom surfaces 1082 b, 1083 b of the second and third top electrodes 1082, 1083 may overlap with corners Cac2 f 1 ₁₀₄ and Cac3 e 1 ₁₀₄ of the bottom electrode 104 respectively, where these corners Cac2 f 1 ₁₀₄, Cac3 e 1 ₁₀₄ may lie between the second and third segments 104 s 2, 104 s 3 of the bottom electrode 104. The top surface 104 a of the bottom electrode 104 may overlap with multiple corners of each top electrode 1081-1084, among which the corner Cbce₁₀₈₁ of the first top electrode 1081, the corner Cbde₁₀₈₂ of the second top electrode 1082, the corner Cbdf₁₀₈₃ of the third top electrode 1083 and the corner Cbcf₁₀₈₄ of the fourth top electrode 1084 may be respectively nearest to the corners Cad2 f 1 ₁₀₄, Cac2 f 1 ₁₀₄, Cac3 e 1 ₁₀₄, Cad3 e 1 ₁₀₄ of the bottom electrode 104.

Accordingly, as shown in FIGS. 33A and 33B, electric field strengths may be higher between the corners Cbce₁₀₈₁, Cbde₁₀₈₂, Cbdf₁₀₈₃, Cbcf₁₀₈₄ of the first, second, third and fourth top electrodes 1081-1084 and the respective corners Cad2 f 1 ₁₀₄, Cac2 f 1 ₁₀₄, Cac3 e 1 ₁₀₄, Cad3 e 1 ₁₀₄ of the bottom electrode 104 as compared to at other parts of the memory device 3200. Conducting filaments may thus be formed and confined between the corners Cbce₁₀₈₁, Cbde₁₀₈₂, Cbdf₁₀₈₃, Cbcf₁₀₈₄ of the first, second, third and fourth top electrodes 1081-1084 and the corners Cad2 f 1 ₁₀₄, Cac2 f 1 ₁₀₄, Cac3 e 1 ₁₀₄, Cad3 e 1 ₁₀₄ of the bottom electrode 104 respectively.

Referring to FIG. 34, the memory device 3400 may include a bottom electrode 104 that may be a cuboid having an elongate cuboidal hole therethrough. In particular, the bottom electrode 104 may include first, second, third and fourth segments 104 s 1, 104 s 2, 104 s 3, 104 s 4, where the first and third segments 104 s 1, 104 s 3 may be substantially parallel to each other. The second and fourth segments 104 s 2, 104 s 4 may lie between the first and third segments 104 s 1, 104 s 3, and may be substantially parallel to each other and substantially perpendicular to the first and third segments 104 s 1, 104 s 3. The bottom electrode 104 may thus further include first and second left surfaces 104 c 1, 104 c 2, first and second right surfaces 104 d 1, 104 d 2, first and second front surfaces 104 e 1, 104 e 2, and first and second back surfaces 104 f 1, 104 f 2. The bottom surfaces 1081 b, 1082 b, 1083 b, 1084 b of the first, second, third and fourth top electrodes 1081-1084 may overlap with corners Cad2 e 2 ₁₀₄, Cac2 e 2 ₁₀₄, Cac2 f 1 ₁₀₄, Cad2 f 1 ₁₀₄ of the bottom electrode 104, respectively. The corner Cad2 e 2 ₁₀₄ may lie between the first and second segments 104 s 1, 104 s 2, the corner Cac2 e 2 ₁₀₄ may lie between the second and third segments 104 s 2, 104 s 3, the corner Cac2 f 1 ₁₀₄ may lie between the third and fourth segments 104 s 3, 104 s 4 and the corner Cad2 f 1 ₁₀₄ may lie between the first and fourth segments 104 s 1, 104 s 4. The top surface 104 a of the bottom electrode 104 may overlap with multiple corners of each top electrode 1081-1084. Out of these corners, the corner Cbcf₁₀₈₁ of the first top electrode 1081, the corner Cbdf₁₀₈₂ of the second top electrode 1082, the corner Cbde₁₀₈₃ of the third top electrode 1083 and the corner Cbce₁₀₈₄ of the fourth top electrode 1084 may be nearest to the corners Cad2 e 2 ₁₀₄, Cac2 e 2 ₁₀₄, Cac2 f 1 ₁₀₄ and Cad2 f 1 ₁₀₄ of the bottom electrode 104, respectively.

Accordingly, as shown in FIGS. 35A and 35B, electric field strengths may be higher between the corners Cbcf₁₀₈₁, Cbdf₁₀₈₂, Cbde₁₀₈₃, Cbce₁₀₈₄ of the first, second, third and fourth top electrodes 1081-1084 and the respective corners Cad2 e 2 ₁₀₄, Cac2 e 2 ₁₀₄, Cac2 f 1 ₁₀₄, Cad2 f 1 ₁₀₄ of the bottom electrode 104 as compared to at other parts of the memory device 3400. Conducting filaments may thus be formed and confined between the corners Cbcf₁₀₈₁, Cbdf₁₀₈₂, Cbde₁₀₈₃, Cbce₁₀₈₄ of the first, second, third and fourth top electrodes 1081-1084 and the corners Cad2 e 2 ₁₀₄, Cac2 e 2 ₁₀₄, Cac2 f 1 ₁₀₄, Cad2 f 1 ₁₀₄ of the bottom electrode 104, respectively.

FIG. 36 and FIG. 37 respectively show simplified top views of memory devices 3600, 3700 according to alternative non-limiting embodiments. The memory devices 3600, 3700 may be 1T8R memory devices.

As shown in FIGS. 36-37, both the memory devices 3600, 3700 may include a single bottom electrode 104 and eight top electrodes 1081-1088 over the bottom electrode 104. Each top electrode 1081-1088 may be a cuboid having surfaces similar to the surfaces 108 a-108 f of the top electrode 108 of the memory device 100. For clarity of illustration, the surfaces of each top electrode 1081-1088 are not labelled in FIGS. 36 and 37. The bottom electrodes 104 of the memory devices 3600, 3700 may be of different shapes.

Referring to FIG. 36, the bottom electrode 104 of the memory device 3600 may include first to ninth segments 104 s 1-104 s 9. The first segment 104 s 1 may be a rectangular segment, and the second to ninth segments 104 s 2-104 s 9 may be side segments arranged perpendicular to and along a length of the first segment 104 s 1. In particular, the second to fifth segments 104 s 2-104 s 5 and the sixth to ninth segments 104 s 6-104 s 9 may be on opposite sides of the width of the first segment 104 s 1. Accordingly, as shown in FIG. 36, the bottom electrode 104 may include first to eighth front surfaces 104 e 1-104 e 8, first to eighth back surfaces 104 f 1-104 f 8, a left surface 104 c and a right surface 104 d.

As shown in FIG. 36, the bottom surfaces 1081 b-1088 b of the top electrodes 1081-1088 may overlap with the corners Cd8 f 5 ₁₀₄, Cd6 f 6 ₁₀₄, Cd4 f 7 ₁₀₄, Cd2 f 8 ₁₀₄, Cd9 e 5 ₁₀₄, Cd7 e 6 ₁₀₄, Cd5 e 7 ₁₀₄, Cd3 e 8 ₁₀₄ of the bottom electrode 104, respectively. In other words, each top electrode 1081-1084 may be arranged over a corner Cd8 f 5 ₁₀₄, Cd6 f 6 ₁₀₄, Cd4 f 7 ₁₀₄, Cd2 f 8 ₁₀₄, Cd9 e 5 ₁₀₄, Cd7 e 6 ₁₀₄, Cd5 e 7 ₁₀₄, Cd3 e 8 ₁₀₄ between two adjacent segments 104 s 1-104 s 9 of the bottom electrode 104. Further, the top surface 104 a of the bottom electrode 104 may overlap with multiple corners of each top electrode 1081-1088, among which the corners Cce₁₀₈₁, Cce₁₀₈₂, Cce₁₀₈₃, Cce₁₀₈₄, Ccf₁₀₈₅, Ccf₁₀₈₆, Ccf₁₀₈₇, Ccf₁₀₈₈ of the first to eighth top electrodes 1081-1088 may be nearest to the corners Cd8 f 5 ₁₀₄, Cd6 f 6 ₁₀₄, Cd4 f 7 ₁₀₄, Cd2 f 8 ₁₀₄, Cd9 e 5 ₁₀₄, Cd7 e 6 ₁₀₄, Cd5 e 7 ₁₀₄, Cd3 e 8 ₁₀₄ of the bottom electrode 104 respectively. Accordingly, conducting filaments may be formed and confined between the corners Cce₁₀₈₁, Cce₁₀₈₂, Cce₁₀₈₃, Cce₁₀₈₄, Ccf₁₀₈₅, Ccf₁₀₈₆, Ccf₁₀₈₇, Ccf₁₀₈₈ of the first to eight top electrodes 1081-1088 and the corners Cd8 f 5 ₁₀₄, Cd6 f 6 ₁₀₄, Cd4 f 7 ₁₀₄, Cd2 f 8 ₁₀₄, Cd9 e 5 ₁₀₄, Cd7 e 6 ₁₀₄, Cd5 e 7 ₁₀₄, Cd3 e 8 ₁₀₄ of the bottom electrode 104, respectively.

Referring to FIG. 37, the bottom electrode 104 of the memory device 3700 may include first to fifth segments 104 s 1-104 s 5. The first segment 104 s 1 may be a rectangular segment, and the second to fifth segments 104 s 2-104 s 5 may be arranged substantially perpendicular to and along a length of the first segment 104 s 1. The second to third segments 104 s 2, 104 s 3 and the fourth to fifth segments 104 s 4, 104 s 5 may be arranged on opposite sides of the width of the first segment 104 s 1. As shown in FIG. 37, the bottom surfaces 1081 b-1088 b of the top electrodes 1081-1088 may overlap with the corners Cc2 f 3 ₁₀₄, Cd4 f 4 ₁₀₄, Cc4 f 4 ₁₀₄, Cd2 f 5 ₁₀₄, Cc3 e 3 ₁₀₄, Cd5 e 4 ₁₀₄, Cc5 e 4 ₁₀₄, Cd3 e 5 ₁₀₄ of the bottom electrode 104, respectively. In other words, each top electrode 1081-1084 may be arranged over a corner Cc2 f 3 ₁₀₄, Cd4 f 4 ₁₀₄, Cc4 f 4 ₁₀₄, Cd2 f 5 ₁₀₄, Cc3 e 3 ₁₀₄, Cd5 e 4 ₁₀₄, Cc5 e 4 ₁₀₄, Cd3 e 5 ₁₀₄ between two adjacent segments 104 s 1-104 s 5 of the bottom electrode 104. Further, the top surface 104 a of the bottom electrode 104 may overlap with multiple corners of each top electrode 1081-1088, among which the corners Cde₁₀₈₁, Cce₁₀₈₂, Cde₁₀₈₃, Cce₁₀₈₄, Cdf₁₀₈₅, Ccf₁₀₈₆, Cdf₁₀₈₇, Ccf₁₀₈₈ of the first to eighth top electrodes 1081-1088 may be nearest to the corners Cc2 f 3 ₁₀₄, Cd4 f 4 ₁₀₄, Cc4 f 4 ₁₀₄, Cd2 f 5 ₁₀₄, Cc3 e 3 ₁₀₄, Cd5 e 4 ₁₀₄, Cc5 e 4 ₁₀₄, Cd3 e 5 ₁₀₄ of the bottom electrode 104, respectively. Accordingly, conducting filaments may be formed and confined between the corners Cde₁₀₈₁, Cce₁₀₈₂, Cde₁₀₈₃, Cce₁₀₈₄, Cdf₁₀₈₅, Ccf₁₀₈₆, Cdf₁₀₈₇, Ccf₁₀₈₈ of the first to eighth top electrodes 1081-1088 and the corners Cc2 f 3 ₁₀₄, Cd4 f 4 ₁₀₄, Cc4 f 4 ₁₀₄, Cd2 f 5 ₁₀₄, Cc3 e 3 ₁₀₄, Cd5 e 4 ₁₀₄, Cc5 e 4 ₁₀₄, Cd3 e 5 ₁₀₄ of the bottom electrode 104, respectively.

FIG. 38A shows a memory structure 3800 (or memory array 3800) including a plurality of memory devices 600 a, 600 b substantially similar to the memory device 600 described with reference to FIGS. 6A to 6C (with substantially similar top and bottom electrodes 104 a, 104 b, 108 a, 108 b), and FIG. 38B shows a memory structure 3801 (or memory array 3801) including a plurality of memory devices 900 a, 900 b substantially similar to the memory device 900 described with reference to FIGS. 9A to 9C (with substantially similar top and bottom electrodes 104 a, 104 b, 108 a, 108 b).

In the memory structure 3800, a separation 3802 between a top electrode 108 a of a first memory device 600 a and a bottom electrode 104 b of a second memory device 600 b (adjacent to the first memory device 600 a) may be configured to be sufficiently large so as to prevent formation of conducting filaments between the electrodes 108 a, 104 b of the adjacent memory devices 600 a, 600 b. Similarly, in the memory structure 3801, a separation 3808 between a top electrode 108 a of a first memory device 900 a and a bottom electrode 104 b of a second memory device 900 b (adjacent to the first memory device 900 a) may be configured to be sufficiently large so as to prevent formation of conducting filaments between the electrodes 108 a, 104 b of the adjacent memory devices 900 a, 900 b. For example, the separations 3802, 3808 may be greater than 50 nm.

FIG. 38A further shows simulated electric fields formed in the memory structure 3800 when the separation 3802 is greater than 50 nm. In particular, the simulated electric field strength at the edge Ebc₁₀₈ a, Ebc₁₀₈ b of the top electrode 108 a, 108 b of each memory device 600 a, 600 b is about 5.93×10⁸V/m, and the simulated electric field strength at the edge Ead_(104a), Ead_(104b) of the bottom electrode 104 a, 104 b of each memory device 600 a, 600 b is about 2.51×10⁸V/m. As shown in FIG. 38A, the edge Ebd_(108a) of the top electrode 108 a of the first memory device 600 a is nearest to the second memory device 600 b, and the edge Eac_(104b) of the bottom electrode 104 b of the second memory device 600 b is nearest to the first memory device 600 a. The simulated electric field strength at the edge Ebd_(108a) is about 4.60×10⁷V/m and the simulated electric field strength at the edge Eac_(104b) is about 4.50×10⁷V/m. With these electric field strengths as compared to the electric field strengths at the edges Ebc_(108a), Ebc_(108b), Ead_(104a), Ead_(104b) in the memory devices 600 a, 600 b, formation of conducting filaments between the edges Ebd_(108a), Eac_(104b) of the adjacent memory devices 600 a, 600 b may be unlikely.

FIG. 38B further shows simulated electric fields formed in the memory structure 3801 when the separation 3808 is greater than 50 nm. As shown in FIG. 38B, the edge Ebd_(108a) of the top electrode 108 a of the first memory device 900 a may be nearest to the second memory device 900 b and the edge Eac_(104b) of the bottom electrode 104 b of the second memory device 900 b may be nearest to the first memory device 900 a. Similarly, formation of conducting filaments between these edges Ebd₁₀₈ a, Eac_(104b) may also be unlikely due to the difference in the electric field strengths at these edges Ebd_(108a), Eac_(104b) and at the edges Ebc₁₀₈ a, Ead₁₀₄ a, Ebc₁₀₈ b, Ead_(104b) of the memory devices 900 a, 900 b.

Although FIGS. 38A and 38B show each memory structure 3800, 3801 as being formed of a same type of memory device 600 a, 600 b/900 a, 900 b, in alternative non-limiting embodiments, memory structures formed of different types of memory devices may be provided. Further, the memory devices forming the memory structures may include any one of the memory devices 100-3700 as described above. The memory structures may also include any type of structure, such as, but not limited to a cross-bar structure.

The above-described memory devices 400-3700 may be fabricated using a process similar to that shown in FIGS. 3A to 3D, where the process may be a CMOS compatible stack process. In addition, the performance of the memory devices 100-3700 may be robust to inaccuracies arising from the fabrication processes (e.g. lithography misalignment/unalignment), since conducting filaments may still be formed even with the lateral offset in positions of the top and bottom electrodes 108, 104.

Further, as described above, in each of the memory devices 100-3700, electric field strengths may be enhanced at particular edges or corners. This can reduce the switching voltages of the memory devices 100-3700 and can also help to better confine the conducting filaments. The improved confinement of the conducting filaments may in turn help to reduce the stochasticity of their formation thus, reducing the variability of the resistance of the switching layers 106 and the memory devices 100-3700 especially when the memory devices 100-3700 are in the HRS. Accordingly, the cycle-to-cycle and device-to-device variability of the memory devices 100-3700 may be reduced, and the scalability of the memory devices 100-3700 may be improved. In particular, conducting filaments may be better confined between corners of the top and bottom electrodes 108, 104 (e.g. corners Cbcf₁₀₈, Cade₁₀₄ of the memory device 400) than between edges of the top and bottom electrodes 108, 104 (e.g. between edges Ebc₁₀₈, Ead₁₀₄ of the memory device 100).

The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein. Scope of the invention is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein. 

The invention claimed is:
 1. A resistive random access memory (RRAM) device comprising: a base insulating layer; a bottom electrode arranged completely within the base insulating layer, wherein a top surface of the bottom electrode and a top surface of the base insulating layer are substantially coplanar; a substantially planar switching layer arranged over the base insulating layer; and a top electrode arranged over the switching layer, wherein the top electrode is substantially planar along an entire length of the top electrode, and the top electrode is arranged in a laterally offset position relative to the bottom electrode.
 2. The RRAM device of claim 1, wherein the top electrode comprises a bottom edge adjoining a bottom surface and a side surface, and the bottom electrode comprises a top edge adjoining a top surface and a side surface; wherein one of the side surface of the top electrode and the side surface of the bottom electrode is a right surface, and the other of the side surface of the top electrode and the side surface of the bottom electrode is a left surface; and wherein the bottom edge of the top electrode and the top edge of the bottom electrode at least partially extend along a same vertical plane.
 3. The RRAM device of claim 2, wherein a front surface of the top electrode and a front surface of the bottom electrode at least partially extend along a same vertical plane; wherein the front surface of the top electrode and the front surface of the bottom electrode face a same direction; and wherein the front surface of the top electrode adjoins the side surface of the top electrode and the front surface of the bottom electrode adjoins the side surface of the bottom electrode respectively.
 4. The RRAM device of claim 2, wherein a front surface of the top electrode and a front surface of the bottom electrode at least partially extend along different vertical planes substantially parallel to and laterally spaced apart from each other; wherein the front surface of the top electrode and the front surface of the bottom electrode face a same direction; and wherein the front surface of the top electrode adjoins the side surface of the top electrode and the front surface of the bottom electrode adjoins the side surface of the bottom electrode respectively.
 5. The RRAM device of claim 4, wherein a corner of the top electrode is vertically aligned with a corner of the bottom electrode; wherein one of the corner of the top electrode and the corner of the bottom electrode adjoins a front surface with two other surfaces of the electrode, and the other of the corner of the top electrode and the corner of the bottom electrode adjoins a back surface with two other surfaces of the electrode.
 6. The RRAM device of claim 1, wherein the top electrode comprises a bottom edge adjoining a bottom surface and a side surface, and the bottom electrode comprises a top edge adjoining a top surface and a side surface, wherein one of the side surface of the top electrode and the side surface of the bottom electrode is a right surface, and the other of the side surface of the top electrode and the side surface of the bottom electrode is a left surface; and wherein the bottom edge of the top electrode and the top edge of the bottom electrode at least partially extend along different vertical planes laterally offset from each other.
 7. The RRAM device of claim 1, wherein the switching layer is arranged planarly over and across the base insulating layer and the bottom electrode, and the bottom surface of the top electrode partially overlaps with the top surface of the bottom electrode.
 8. The RRAM device of claim 7, wherein a front surface of the top electrode and a front surface of the bottom electrode at least partially extend along a same vertical plane, wherein the front surface of the top electrode and the front surface of the bottom electrode face a same direction.
 9. The RRAM device of claim 7, wherein a front surface of the top electrode and a front surface of the bottom electrode at least partially extend along different vertical planes substantially parallel to and laterally spaced apart from each other, wherein the front surface of the top electrode and the front surface of the bottom electrode face a same direction.
 10. The RRAM device of claim 9, wherein the top surface of the bottom electrode overlaps with a corner of the top electrode, and the bottom surface of the top electrode overlaps with a corner of the bottom electrode; wherein one of the corner of the top electrode and the corner of the bottom electrode adjoins a front surface with two other surfaces of the electrode, and the other of the corner of the top electrode and the corner of the bottom electrode adjoins a back surface with two other surfaces of the electrode.
 11. The RRAM device of claim 10, wherein the bottom electrode comprises a first segment and a second segment substantially perpendicular to each other, and wherein the corner of the bottom electrode lies between the first segment and the second segment.
 12. The RRAM device of claim 1, wherein the bottom surface of the top electrode and the top surface of the bottom electrode have a same shape.
 13. The RRAM device of claim 1, wherein the bottom surface of the top electrode and the top surface of the bottom electrode have different shapes.
 14. The RRAM device of claim 1, wherein the top electrode is in direct contact with the switching layer, and the bottom surface of the top electrode and the top surface of the bottom electrode are laterally spaced apart.
 15. The RRAM device of claim 14, wherein a front surface of the top electrode and a front surface of the bottom electrode at least partially extend along a same vertical plane, wherein the front surface of the top electrode and the front surface of the bottom electrode face a same direction.
 16. The RRAM device of claim 14, wherein a front surface of the top electrode and a front surface of the bottom electrode at least partially extend along different vertical planes substantially parallel to and laterally spaced apart from each other, wherein the front surface of the top electrode and the front surface of the bottom electrode face a same direction.
 17. The RRAM device of claim 1, further comprising at least one additional top electrode arranged over the switching layer in a laterally offset position relative to the bottom electrode, wherein each of the at least one additional top electrode is substantially planar.
 18. A resistive random access memory (RRAM) device comprising: a base insulating layer; a bottom electrode arranged completely within the base insulating layer, wherein a top surface of the bottom electrode and a top surface of the base insulating layer are substantially coplanar; a substantially planar switching layer arranged over the base insulating layer; and a top electrode arranged over the switching layer, wherein the top electrode is substantially planar along an entire length of the top electrode, and the top electrode is arranged in a laterally offset position relative to the bottom electrode; wherein a bottom edge between a bottom surface and a side surface of the top electrode, and a top edge between a top surface and a side surface of the bottom electrode are spaced apart by a distance at least equal to a thickness of the switching layer.
 19. The RRAM device of claim 18, wherein the bottom edge of the top electrode and the top edge of the bottom electrode at least partially extend along different vertical planes substantially parallel to and laterally spaced apart from each other.
 20. A method of fabricating a resistive random access memory (RRAM) device, the method comprising: providing a base insulating layer; forming a bottom electrode completely within the base insulating layer, wherein a top surface of the bottom electrode and a top surface of the base insulating layer are substantially coplanar; forming a substantially planar switching layer over the base insulating layer; and forming a top electrode over the switching layer in a laterally offset position relative to the bottom electrode, wherein the top electrode is substantially planar along an entire length of the top electrode. 